News Column

Patent Issued for System and Process for Automatic Clock Routing in an Application Specific Integrated Circuit

July 16, 2014

By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Berry, Clay (Garland, TX); McDonald, Timothy J. (Austin, TX), filed on February 8, 2013, was published online on July 1, 2014.

The patent's assignee for patent number 8769463 is Nvidia Corporation (Santa Clara, CA).

News editors obtained the following quote from the background information supplied by the inventors: "Integrated circuits (IC) are miniaturized electronic circuits that are typically manufactured from a semiconductor material. Due to the reliability of integrated circuits and developments within the industry that allow ICs to be mass produced, the usage of integrated circuits has become ubiquitous in the manufacture of many commercial electronics equipment produced today and have contributed significantly to the proliferation and development of the electronics industry.

"Application-specific integrated circuits (ASICs) are integrated circuits designed and customized for a particular use. Often, one or more ASICs are implemented on or as part of an electronic hardware chip. In a typical integrated circuit design, disparate and independent units (or 'modules') of logic are clustered with units having similar function and/or purpose to form separate, specialized partitions within the chip. Many integrated circuits will use one or more clock signals in order to synchronize the modules of the circuit and to account for propagation delays across the chip. This clock signal may be generated by a clock source (such as a phase-locked loop), and directed and propagated through the partitions in a chip via clock routes between adjacent partitions.

"In typical implementations, routes connecting partitions and clock sources may be pre-determined and implemented by routing macros among the adjacent partitions. Conventionally, these routing macros are embedded and intrinsic to the partitions, wherein a single partition may have multiple macros. For example, a common configuration comprises partitions with four or more macros, oriented according to compass directions (e.g., North, South, West and/or Center and East). For exceptionally large partitions, additional mid-partition macros may also be included. Global clock routing tools layout the clock sources based on a grid that is overlaid onto the chip. The overall clock layout grid may not be associated with the underlying partition, so the placement of the clock source may become problematic within the partition layout.

"According to conventional IC design methodology, each clock signal may be programmed to take a particular route once the 'floor plan' of the partitions is known (e.g., set by design). Because the sizes and shapes of partitions may vary according to the particular configurations of logic there is a tendency for the partitions to be shaped irregularly and/or asymmetrically due to ad hoc customization. As a consequence, programming the routing between partitions must be performed manually, and every route is independently specified for each step in the route. Naturally, this can be a very time consuming and effort-intensive procedure. As ICs become more complex (e.g., designed to include more partitions), the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult.

"Further complicating the matter, the inconsistency of partition sizes and shapes can add to the complexity of manually programming specific routes as well as resulting in severely inconsistent hop lengths, which, when combined with human error, increases the potential for sub-optimal clock routes or ineffective signal delivery. Moreover, chip designs may change between the initial floor planning stage and the completion of a final design within the design process. Frequently, the size and/or shape of one or more partitions may change dramatically, and, because the ability of a clock routing macro to propagate a signal is finite, significant alterations may result in transition violation issues as an originally adequate clock routing macro may no longer be sufficient to propagate a signal to the next destination in a route, thereby rendering the original clock routing macro layout obsolete and requiring significant reprogramming of the corresponding one or more clock routes. In some cases, the modification of the partitions may occur even after the macros have been embedded to the macro. In such instances, post design change orders may be required, which may contribute heavily to unnecessary delays and additional labor costs."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "This Summary is provided to introduce a selection of concepts in a simplified form that is further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

"Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks throughout an ASIC of various sizes and compositions. According to one embodiment, clock sources and sinks are mapped to grid point locations and then a novel grid routing process is performed to link them together. According to embodiments of the claimed invention, any shape of the grid may be accommodated using standard rectangular grid dimensions (e.g., 4.times.6, 5.times.5) and then identifying blockages where customized partitions, hard macros or highly congested areas of logic through which routes may be undesirable.

"According to further embodiments, a method for grid routing is provided wherein blockages are opportunistically bypassed and detoured around, as required. Grid points are sized from several available buffer arrays based on the number of clock signals that are determined to pass through it. Clock signal paths from common start points are merged to reduce power, decrease clock skew, and minimize routing congestion. According to some embodiments, the grid of clock routing macros is defined at the register-transfer level (RTL) of the logic design phase. When the physical implementation is created, the grid points are overlaid on the chip physical layout. The clock routing macros at each grid point are pushed into the partition that covers that grid point."

For additional information on this patent, see: Berry, Clay; McDonald, Timothy J.. System and Process for Automatic Clock Routing in an Application Specific Integrated Circuit. U.S. Patent Number 8769463, filed February 8, 2013, and published online on July 1, 2014. Patent URL:

Keywords for this news article include: Electronics, Nvidia Corporation.

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Source: Electronics Newsweekly

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