News Column

Patent Issued for Switch Architecture at Low Supply Voltages

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Mishra, Vineet (Karnataka, IN); Thinakaran, Rajavelu (Karnataka, IN), filed on March 5, 2014, was published online on July 1, 2014.

The patent's assignee for patent number 8766700 is Texas Instruments Incorporated (Dallas, TX).

News editors obtained the following quote from the background information supplied by the inventors: "Electronic switches are found in many electronic applications. For example analog-to-digital converters (ADCs), or the like, is one application in which electronic switches are widely used. Many other general applications abound. An example of a complementary metal-oxide semiconductor (CMOS) switch 10 of one type of electronic switch described herein is shown in FIG. 1, to which reference is now made.

"The switch 10 includes a p-channel metal-oxide semiconductor MOS (PMOS) device 12 and an n-channel metal-oxide semiconductor (NMOS) device 14. The PMOS device 12 has its source connected to an input node 16 and its drain connected to an output node 18. The gate of the PMOS device 12 is connected to a reference potential, or ground 22. The NMOS device 14 has its drain connected to the input node 16 and its source connected to the output node 18. The gate of the NMOS device 14 is connected to an analog voltage supply source (VDD) 22.

"In operation, when the voltage between the input node 16 and ground 20 is above V.sub.tp (V.sub.tp is the threshold voltage of the PMOS device 12), the PMOS device 12 will conduct. Similarly, when the voltage between VDD 22 and the input node 16 is above the threshold voltage V.sub.tn of the NMOS device 14, the NMOS device 14 will conduct.

"One of the conditions that is often encountered is a high rail-to-rail signal voltage. A high supply range between 1.7 V and 3.6 V must be supported in many applications. However, the case of a CMOS switch, the threshold voltage of the PMOS device 12 plus the threshold voltage of the NMOS device 14 (V.sub.tp+V.sub.tn) may be higher than the difference in voltage between VDD and ground. As a result, a large switch area may be required. Another condition that may be encountered in some applications is that a supply boost switch may be unusable due to a very large clock time period, or a unavailable usable clock signal.

"In many applications, the switch may be operated with a sampling signal, such as, for instance, in the example CMOS switch circuit 30 shown in FIG. 2, to which reference is now additionally made. The CMOS switch circuit 30 includes an NMOS device 34 and a PMOS device 36 between the input node 38 and output node 40. A variable voltage 32 is applied to the input node 38. The sampling signal (SAMP) is applied to the gate of the NMOS device 34 and an inverted sampling signal (SAMPZ) is applied to the gate of the PMOS device 36. The output from the switch 30 is applied across a capacitor 42 in the output node 40 and connected to an output by a switch 44 that is switched at a sampling frequency.

"However, in many applications, for example in analog-to-digital converters (ADCs), a sampling instant 45 may be provided by an off-chip signal that is asynchronous to an internal analog-to-digital (ADC) conversion clock 46. Synchronizing the off-chip asynchronous sampling clock to an internal ADC clock and using that to operate a boost switch can cause a phase delay 48 in sampling, shown in FIG. 3. The phase delay 48 may result in a sampling error and a degraded signal-to-noise ratio (SNR). If the sampling signal is asynchronous to the ADC clock, it may lead to kick-back at the input before sampling."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "An embodiment of a sampled CMOS switch for connection between input and output nodes includes first and second MOS devices in series between input and output nodes of the switch. The first and second NMOS devices are activated by a sample signal. A pair of extended drain MOS devices is connected in a 'T' configuration between the input and output nodes. The extended drain MOS devices are activated by an inverted sample signal. In one embodiment, the first and second MOS devices are NMOS devices and the pair of extended drain MOS devices comprises DEPMOS devices. In another embodiment, the DEPMOS devices are a part of a feedback circuit that includes a third NMOS device and a current source connected between an analog voltage source and a reference potential. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal.

"Another embodiment of a sampled CMOS switch for connection between input and output nodes has first and second NMOS devices in series between the input and output nodes. The first and second NMOS devices are activated by a sample signal to connect the input node to the output node. The sampled CMOS switch has a feedback circuit which includes a pair of DEPMOS devices in a 'T' configuration between the input and output nodes. The pair of DEPMOS devices are activated by an inverted sample signal. The low voltage DEPMOS device has a low V.sub.t that solves the problem of V.sub.tp+V.sub.tn>VDD-GND. However due to the gate oxide reliability of low voltage DEPMOS devices, it needs to be protected by a third NMOS used in feedback circuit. Thus, the feedback circuit includes the third NMOS device and a current source between an analog voltage source and a reference potential. The third NMOS device is controlled by a signal on the input node. The feedback circuit additionally has a switch to switchably connect an analog voltage source to a source of the third NMOS device and to gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. In one embodiment, the first and second NMOS devices are high voltage devices and the DEPMOS devices are low voltage devices with low threshold voltages. This ensures that the sum of threshold voltage of high voltage NMOS and low voltage DEPMOS (V.sub.tp+V.sub.tn) is less than difference between supply VDD and ground.

"A method embodiment for protecting gate oxide insulation of low voltage DEPMOS transistors of a sampled CMOS switch from high voltage damage includes connecting the MOS transistors in series between the input and output nodes. The method also includes connecting a pair of extended drain MOS devices connected in a 'T' configuration between the input and output nodes. The pair of extended drain MOS devices are activated by an inverted sample signal. In one embodiment, the first and second MOS transistors are NMOS devices and the pair of extended drain MOS devices comprise DEPMOS devices. In one embodiment of the method, a third high-voltage NMOS device and a current source are connected between an analog voltage source and a reference potential. The third NMOS device is controlled by a signal on the input node. A switch is provided that is operable to switchably connect an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of the inverted sample signal."

For additional information on this patent, see: Mishra, Vineet; Thinakaran, Rajavelu. Switch Architecture at Low Supply Voltages. U.S. Patent Number 8766700, filed March 5, 2014, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766700.PN.&OS=PN/8766700RS=PN/8766700

Keywords for this news article include: Electronics, High Voltage, Semiconductor, Texas Instruments Incorporated.

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Source: Electronics Newsweekly


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