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Patent Issued for Shallow Trench Isolation Recess Repair Using Spacer Formation Process

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Cai, Ming (Hopewell Junction, NY); Li, Xi (Somers, NY); Tamweber, Jr., Frank D. (Poughkeepsie, NY), filed on October 28, 2010, was published online on July 1, 2014.

The assignee for this patent, patent number 8765491, is International Business Machines Corporation (Armonk, NY).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to semiconductor device manufacturing and, more particularly, to a structure and method for shallow trench isolation (STI) recess repair prior to silicide processing, using a gate spacer layer.

"A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, a given semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is provided by isolation structures that employ trenches filled with an insulator material (e.g., shallow trench isolation or 'STI' regions).

"In addition, certain inactive areas of a semiconductor device defined by STI regions may also have so called 'dummy' gate structures formed thereon. These dummy gate structures on the STI regions are electrically non-functional, but serve one or more mechanical purposes. For example, substantially planar surfaces within a semiconductor topography may play an important role in fabricating overlying layers and structures. That is, step coverage problems may arise when a material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography.

"In general, a topography having relatively wide regions of material may also be more prone to dishing effects of chemical mechanical polishing (CMP) than a topography having relatively narrow regions of material. Thus, the dummy structures formed on the inactive STI regions of a semiconductor device can contribute to a substantially planar surface, but do not affect the functionality of the device.

"However, during one or more cleaning processes (e.g., DHF/wet clean/Aqua Regia) used in the front-end-of-the-line (FEOL) processing, the STI regions may be subjected to the formation of severe recesses therein. Such recesses may occur, for example, during metal silicide formation on gate, source and drain contacts of a field effect transistor (FET). Unfortunately, a subsequent cap layer (e.g., nitride) that is formed over the silicided transistor devices can be pinched off so as to have a void formed therein, where such voids correspond to locations above the recessed STI. An STI recess therefore introduces a significant challenge for a middle-of-the-line (MOL) nitride layer to fill the gap between adjacent gates, especially at sub-32 nanometer (nm) ground rules. An incomplete gap fill, also known as a tungsten (W) subway void defect, remains a yield and reliability concern, even on electrically non-functional STI regions."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In one aspect, a method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate; and subjecting the spacer layer to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and wherein a horizontal fill portion of the spacer remains in one more recesses present in the STI region so as to substantially planarize the STI regions prior to subsequent material deposition thereon.

"In another aspect, a method of forming a semiconductor device includes forming a nitride spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate; subjecting the nitride spacer layer to a directional etch so as to form nitride sidewall spacers adjacent the plurality of transistor gate structures, wherein a horizontal fill portion of the nitride spacer layer remains in one more recesses present in the STI region so as to substantially planarize the STI regions prior to subsequent material deposition thereon; and wherein the nitride spacer layer is formed at an initial thickness sufficient to both facilitate sidewall spacer formation and to prevent pinch off of the spacer layer at locations corresponding to the one or more recesses.

"In another aspect, a method of forming a semiconductor device includes forming a nitride spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate; masking the nitride spacer layer so as to protect portions of the nitride spacer layer over the STI regions; and subjecting exposed portions of the nitride spacer layer over the active regions to a directional etch so as to form nitride sidewall spacers adjacent the plurality of transistor gate structures; wherein the nitride spacer layer is formed at an initial thickness sufficient to both facilitate sidewall spacer formation in the active area and to prevent pinch off of the spacer layer at locations corresponding to one or more recesses present in the STI regions.

"In another aspect, a semiconductor device includes a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate; at least a portion of the plurality of transistor gate structures having sidewall spacers formed adjacent thereto; and one more recesses present in the STI region being filled with horizontal portions material used to form the sidewall spacers so as to substantially planarize the STI regions."

For more information, see this patent: Cai, Ming; Li, Xi; Tamweber, Jr., Frank D.. Shallow Trench Isolation Recess Repair Using Spacer Formation Process. U.S. Patent Number 8765491, filed October 28, 2010, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765491.PN.&OS=PN/8765491RS=PN/8765491

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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