News Column

Patent Issued for Semiconductor Wafer Processing Method

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Disco Corporation (Tokyo, JP) has been issued patent number 8765579, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Kim, Youngsuk (Ota-Ku, JP); Harada, Shigenori (Ota-Ku, JP).

This patent was filed on June 20, 2012 and was published online on July 1, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a semiconductor wafer processing method for manufacturing a stacked device chip composed of a plurality of stacked semiconductor devices.

"In a semiconductor device fabrication process, a plurality of crossing division lines called streets are formed on the front side of a semiconductor wafer to thereby partition a plurality of regions where devices such as ICs and LSIs are respectively formed. The semiconductor wafer is divided into chips along the division lines, thereby manufacturing a plurality of individual semiconductor devices. The semiconductor devices thus manufactured are widely used in various electrical equipment.

"With a reduction in size and thickness of electrical equipment in recent years, it is required to also reduce the size and thickness of a semiconductor device package, and high-density mounting is therefore required. As a technique for integrating a plurality of semiconductor devices in one package, there is a three-dimensional mounting technique such that a plurality of semiconductor device chips are stacked in a vertical direction. In a conventional three-dimensional mounting technique, the semiconductor device chips are connected to each other by wire bonding or the semiconductor device chips and an interposer are connected to each other by wire bonding. The connection by wire bonding has a problem such that an inductance is increased by the length of wires and this technique is therefore unsuitable for high-speed transmission of signals. Another problem on wire bonding is such that the semiconductor device chips must be stacked without the contact of the wires, causing the difficulty in reducing the size of the package.

"As a new three-dimensional mounting technique, there has recently been developed a stacking technique such that a plurality of semiconductor device chips are stacked on a semiconductor device wafer (Chip On Wafer) and a through electrode extending between a semiconductor device of each semiconductor device chip and each semiconductor device of the semiconductor device wafer is formed to connect these semiconductor devices to each other. To reduce the thickness of such a stacked chip package, it is desirable to reduce the thickness of each semiconductor device chip to be stacked on the semiconductor device wafer to 50 .mu.m or less, for example. For the purposes of facilitating the handling of the semiconductor device wafer and reducing the risk of damage to the semiconductor device wafer, the semiconductor device wafer is attached to a substrate before reducing the thickness of the semiconductor device wafer and performing various processings.

"In forming the through electrode, it is necessary to perform heat treatment such as an insulating film forming step including heating at about 450.degree. C. and a reflow step including heating at about 200.degree. C. Conventionally, after the semiconductor device wafer is attached to the substrate such as a glass substrate by using a heat-resistant adhesive, the semiconductor device wafer is subjected to a metal film forming step and heat treatment."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "In general, there is a problem such that the heat-resistant adhesive is expensive. Further, when the semiconductor device wafer is attached through the adhesive to the substrate, the adhesive may remain on the device surface of the semiconductor device wafer after performing the heat treatment. Further, the substrate is required to have high flatness, so that it is very expensive. Accordingly, a process without using such a substrate is desired.

"Each semiconductor device chip to be stacked in forming the stacked device package is required to have a thickness of 50 .mu.m or less, for example. However, such a thin semiconductor device chip is difficult to handle, and there is accordingly a possibility of damage to the chip in stacking.

"It is therefore an object of the present invention to provide a semiconductor wafer processing method which can form a chip stacked wafer having semiconductor devices and semiconductor device chips respectively stacked on the semiconductor devices without using a substrate and without causing damage to the semiconductor device chips.

"In accordance with an aspect of the present invention, there is provided a processing method for a semiconductor wafer having a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral marginal area surrounding the device area, the processing method including a protective tape attaching step of attaching a protective tape to the front side of the semiconductor wafer; a grinding step of grinding the back side of the semiconductor wafer in a central area corresponding to the device area to thereby form a circular recess and an annular projection surrounding the circular recess after performing the protective tape attaching step; a chip stacked wafer forming step of providing a plurality of semiconductor device chips on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer in the condition where the device surface of each semiconductor device chip comes into contact with the bottom surface of the circular recess and filling a filler into the circular recess until reaching a depth corresponding to a finished thickness of each semiconductor device chip to thereby form a chip stacked wafer after performing the grinding step; a thickness reducing step of grinding the back side of the chip stacked wafer to thereby reduce the thickness of each semiconductor device chip to the finished thickness after performing the chip stacked wafer forming step; and a through electrode forming step of forming a through electrode in each semiconductor device of the semiconductor wafer after performing the thickness reducing step.

"Preferably, the processing method further includes a dividing step of dividing the chip stacked wafer along the division lines after performing the through electrode forming step.

"According to the present invention, the annular projection as a reinforcing portion is formed along the outer circumference of the semiconductor wafer by the grinding step. Accordingly, the chip stacked wafer having the semiconductor device chips respectively stacked on the semiconductor devices can be formed without using a substrate. After the semiconductor device chips in their unground condition (thick condition) are respectively stacked on the semiconductor devices, the back side of each semiconductor device chip is ground. Accordingly, handling of each semiconductor device chip in stacking can be made easy to thereby reduce the risk of damage to each semiconductor device chip.

"The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description and appended claims with reference to the attached drawings showing some preferred embodiments of the invention."

For the URL and additional information on this patent, see: Kim, Youngsuk; Harada, Shigenori. Semiconductor Wafer Processing Method. U.S. Patent Number 8765579, filed June 20, 2012, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765579.PN.&OS=PN/8765579RS=PN/8765579

Keywords for this news article include: Electronics, Semiconductor, Disco Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters