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Patent Issued for Semiconductor Devices Including Vertical Channel Transistors and Methods of Manufacturing the Same

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Chung, Hyun-woo (Seoul, KR); Hong, Hyeong-sun (Seongnam-si, KR); Oh, Yong-chul (Suwon-si, KR); Hwang, Yoo-sang (Suwon-si, KR); Baek, Cheol-ho (Yongin-si, KR); Kim, Kang-uk (Seoul, KR), filed on July 19, 2011, was published online on July 1, 2014.

The patent's assignee for patent number 8766354 is Samsung Electronics Co., Ltd. (Gyeonggi-do, KR).

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments of the inventive concepts relate to semiconductor devices and methods of manufacturing the same, and particularly, to semiconductor devices including vertical channel transistors, in which a vertical channel is formed in an active region, and a method of manufacturing the same.

"The greater the degree of integration of a semiconductor device, the smaller the design rules of elements of the semiconductor device. In particular, in the case of semiconductor devices that require a large number of transistors, a channel length decreases as a gate length decreases, which is considered a standard design rule. Accordingly, a vertical channel transistor may increase an effective channel length by increasing the distance between a source and drain of a transistor of a highly-scaled semiconductor device."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Example embodiments of the inventive concepts may provide highly integrated semiconductor devices including buried bit lines and vertical channel transistors. One or more example embodiments of the inventive concepts may provide methods of manufacturing semiconductor devices including vertical channel transistor structures with a fine unit cell size while securing a sufficient process margin during formation of buried bit lines and/or vertical channel transistors.

"According to example embodiments of the inventive concepts, a semiconductor device includes a plurality of active regions disposed apart from each other in a substrate in a first direction and a second direction, a plurality of buried word lines extending in the first direction while facing sidewalls of a first group of active regions arranged in a line in the first direction from among the plurality of active region, upper surfaces of the plurality of buried word lines lower than an upper surface of the substrate, and a plurality of buried bit lines extending in the second direction while contacting sidewalls of a second group of active regions arranged in a line in the second direction from among the plurality of active region. Upper surfaces of the plurality of buried bit lines are lower than the upper surface of the substrate, the first group of active regions including a plurality of pairs of first active regions, a distance between two active regions that constitute a pair of first active regions from among the plurality of pairs of first active regions less than a distance between two adjacent active regions having the plurality of buried bit lines therebetween.

"The plurality of pairs of first active regions may be disposed having two adjacent buried bit lines therebetween. The second group of active regions may include a plurality of pairs of second active regions. A distance between two active regions that constitute a pair of second active regions from among the plurality of second active region, may be less than a distance between two adjacent active regions having the plurality of buried word lines therebetween. The plurality of pairs of second active regions may be arranged having two adjacent buried word lines therebetween. Each of the plurality of buried word lines may face one sidewall of each of the active regions belonging to the first group, and a single-gate transistor including one buried word line from among the plurality of buried word lines may be formed in each of the plurality of active regions. The plurality of buried word lines may be formed in bar shapes extending in the first direction at a side of the first group of active regions.

"Each pair of the plurality of pairs of buried bit lines may be disposed between each of the plurality of pairs of first active regions. A distance between each pair of the plurality of pairs of buried bit lines, may be less than a distance between two adjacent buried bit lines having each pair of the plurality of pairs of first active regions therebetween. Each pair of the plurality of pairs of buried word lines may be disposed between each of the plurality of pairs of second active regions. A distance between each pair of the plurality of pairs of buried word lines, may be less than a distance between two adjacent buried bit lines having each of the plurality of pairs of second active regions therebetween.

"The second group of active regions may include a plurality of second active regions disposed at equal intervals in the second direction. Each of the plurality of buried word lines may face two sidewalls of each of the active regions belonging to the first group, and a double-gate transistor including one buried word line from among the plurality of buried word lines may be formed in each of the plurality of active regions. The plurality of buried word lines may be formed in ring shapes covering the first group of active regions, respectively. Each pair of the plurality of pairs of buried bit lines may be disposed between each of the plurality of pairs of first active regions. A distance between each pair of the plurality of pairs of buried bit lines may be less than a distance between two adjacent buried bit lines having each of the plurality of pairs of first active regions therebetween. The second direction may be perpendicular to the first direction.

"According to other example embodiments of the inventive concepts, a semiconductor device includes a plurality of active regions defined in a substrate by a plurality of first buried patterns, a plurality of second buried patterns, a plurality of third buried patterns, and a plurality of fourth buried patterns, where the plurality of first buried patterns and the plurality of second buried patterns are alternately buried in the substrate in a first direction, and the plurality of third buried patterns and the plurality of fourth buried patterns are buried in the substrate in a second direction. A plurality of buried bit lines are formed on the substrate in such a manner that upper surfaces of the plurality of buried bit lines are lower than an upper surface of the substrate. The plurality of buried bit lines include a plurality of pairs of buried bit lines including two buried bit lines that face each other while including the plurality of first buried patterns therebetween. A plurality of buried word lines are formed on the substrate in such a manner that upper surfaces of the plurality of buried word lines are lower than the upper surface of the substrate and are higher than upper surfaces of the plurality of pairs of buried bit lines. A plurality of first source/drain regions are formed around the plurality of buried bit lines, respectively. A plurality of first source/drain regions are formed around the plurality of buried bit lines on the substrate.

"A third distance between the upper surface of the substrate and lower surfaces of the plurality of third buried patterns and a fourth distance between the upper surface of the substrate and lower surfaces of the plurality of fourth buried patterns, may be less than a first distance between the upper surface of the substrate and lower surfaces of the plurality of first buried patterns. Each of the plurality of pairs of buried bit lines, and two active regions that face each other while including the plurality of second buried patterns therebetween from among the plurality of active regions, may be alternately disposed. The two active regions facing each other while including the plurality of second buried patterns therebetween, may contact one of the plurality of buried bit lines. The plurality of buried word lines may include a plurality of pairs of buried word lines, each pair including two buried word lines that face each other while including the plurality of third buried patterns therebetween.

"Each of the plurality of pairs of buried word lines, and two active regions that face each other while including the plurality of fourth buried patterns therebetween from among the plurality of active regions, may be alternately disposed. The two active regions facing each other while including the plurality of fourth buried patterns therebetween, may face one of the plurality of buried word lines. A thickness of the plurality of buried bit lines extending in a direction from bottom to top of the substrate, may be less than a thickness of the plurality of buried word lines extending in a direction from bottom to top of the substrate.

"According to yet other example embodiments of the inventive concepts, there is provided a method of manufacturing a semiconductor device. In this method, a plurality of first trenches are formed by partially etching a substrate. A plurality of first conductive patterns are formed in the plurality of first trenches in such a manner that a pair of first conductive patterns are disposed in each of the plurality of first trenches. A plurality of first buried patterns are formed in the plurality of first trenches to cover the plurality of first conductive patterns. Then, a plurality of second trenches are formed by etching the substrate between the plurality of first trenches. The plurality of second trenches include a pair of adjacent second trenches having the pair of first conductive patterns therebetween. A plurality of second buried patterns are formed in the plurality of second trenches.

"The forming of the plurality of first conductive patterns may include forming a plurality of conductive layers for filling at least one portion of spaces in the plurality of first trenches therewith, respectively, and dividing each of the plurality of conductive layers into two parts so as to form the plurality of first conductive patterns covering inner sidewalls of the plurality of first trenches, respectively. The method may further include forming a plurality of sacrificial layer patterns on the substrate before the plurality of first trenches are formed. The forming of the plurality of first trenches may include etching the substrate by using the plurality of sacrificial layer patterns as an etch mask. The forming of the plurality of second trenches may include removing the plurality of sacrificial layer patterns, and etching the substrate exposed via regions from which the plurality of sacrificial layer patterns are removed.

"The method may further include forming a plurality of first source/drain regions of a first conductive type by implanting impurity ions into the substrate via bottom surfaces of the plurality of first trenches, before the plurality of first conductive patterns are formed in the plurality of first trenches, and dividing each of the plurality of first source/drain regions into two parts by etching the substrate between a pair of first conductive patterns in each of the plurality of first trenches after the plurality of first conductive patterns are formed in the plurality of first trenches. After each of the plurality of first source/drain regions is divided into two parts, two first source/drain regions may be disposed between two adjacent first trenches from among the plurality of first trenches.

"The forming of the plurality of second trenches may include forming a plurality of second upper trenches having a first depth by etching the substrate to the first depth, forming a plurality of non-floating body (NFB) ion implanting regions of a second conductive type by implanting impurity ions into the substrate via bottom surfaces of the plurality of second upper trenches, each of the plurality of NFB ion implanting regions being located between two first source/drain regions between two adjacent first trenches, and etching the substrate to pass through the plurality of NFB ion implanting regions starting from the bottom surfaces of the plurality of second upper trenches. Here, the second conductive type is different from the first conductive type, and the first depth is less than depths of the plurality of second trenches.

"The method may further include forming a plurality of third trenches by partially etching the plurality of first buried patterns, the plurality of second buried patterns, and the substrate, bottom surfaces of the plurality of third trenches higher than upper surfaces of the plurality of first conductive patterns, forming a plurality of second conductive patterns in the plurality of third trenches in such a manner that a pair of second conductive patterns is disposed in each of the plurality of third trenches, forming a plurality of third buried patterns in the plurality of third trenches to cover the plurality of second conductive patterns, forming a plurality of fourth trenches by partially etching the substrate between the plurality of third trenches. The plurality of fourth trenches include a pair of adjacent fourth trenches having the pair of second conductive patterns therebetween, upper surfaces of the plurality of fourth trenches higher than the upper surfaces of the plurality of first conductive patterns; and forming a plurality of fourth buried patterns in the plurality of fourth trenches.

"After the plurality of third buried patterns are formed and before the plurality of fourth trenches are formed, the method may further include forming a plurality of second source/drain regions of the first conductive type on the substrate by implanting impurity ions into the substrate. The method may further include forming a plurality of second source/drain regions of the first conductive type on the substrate by implanting impurity ions into the substrate, after the plurality of fourth buried patterns are formed in the plurality of fourth trenches. The method may further include forming a body contact line conductive layer below the plurality of fourth trenches, after the plurality of fourth trenches are formed, the plurality of fourth buried patterns formed on the body contact line conductive layer and in the plurality of fourth trenches, respectively. The plurality of first conductive patterns may be a plurality of bit lines. The plurality of second conductive patterns may be a plurality of word lines.

"According to at least one example embodiment of the inventive concepts, a semiconductor device includes active regions spaced apart from each other in first and second directions in a substrate, a plurality of buried word lines extending in the first direction on sidewalls of a first group of the active regions arranged in the first direction, the first group including a first plurality of pairs of the active regions, upper surfaces of the plurality of buried word lines lower than an upper surface of the substrate, and a plurality of buried bit lines extending in the second direction on sidewalls of a second group of the active regions arranged in the second direction, a distance between adjacent active regions of the first group with at least two of the plurality of buried bit lines therebetween greater than a distance between active regions of at least one of the first plurality of pairs, upper surfaces of the plurality of buried bit lines lower than the upper surface of the substrate.

"According to at least one example embodiment of the inventive concepts, a semiconductor device includes a plurality of active regions defined in a substrate by a plurality of first buried patterns, a plurality of second buried patterns, a plurality of third buried patterns, and a plurality of fourth buried patterns, the plurality of first buried patterns and the plurality of second buried patterns alternately buried in the substrate in a first direction, and the plurality of third buried patterns and the plurality of fourth buried patterns buried in the substrate in a second direction, a plurality of buried bit lines including a plurality of pairs of buried bit lines, each pair of buried bit lines including two buried bit lines facing each other, one of the plurality of first buried patterns between the two buried bit lines of each pair of buried bit lines, upper surfaces of the plurality of buried bit lines lower than an upper surface of the substrate, a plurality of buried word lines with upper surfaces between the upper surface of the substrate and upper surfaces of the plurality of pairs of buried bit lines, a plurality of first source/drain regions around the plurality of buried bit lines, and a plurality of second source/drain regions in the plurality of active regions in the substrate.

"According to at least one example embodiment of the inventive concepts, a method of manufacturing a semiconductor device includes forming a plurality of first trenches by partially etching a substrate, forming a plurality of first conductive patterns in the plurality of first trenches such that a pair of first conductive patterns are in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by partially etching the substrate between the plurality of first trenches, the plurality of second trenches including at least one pair of adjacent second trenches with one of the pairs of first conductive patterns therebetween, and forming a plurality of second buried patterns in the plurality of second trenches.

"According to at least one example embodiment of the inventive concepts, a semiconductor device includes a plurality of active regions of a substrate, a plurality of bit lines in the substrate, each of the bit lines connected to at least one of the active regions and a plurality of word lines in the substrate, each of the word lines on a sidewall of at least one of the active regions."

For additional information on this patent, see: Chung, Hyun-woo; Hong, Hyeong-sun; Oh, Yong-chul; Hwang, Yoo-sang; Baek, Cheol-ho; Kim, Kang-uk. Semiconductor Devices Including Vertical Channel Transistors and Methods of Manufacturing the Same. U.S. Patent Number 8766354, filed July 19, 2011, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766354.PN.&OS=PN/8766354RS=PN/8766354

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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