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Patent Issued for Semiconductor Devices Having Dielectric Caps on Contacts and Related Fabrication Methods

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Yuan, Lei (Sunnyvale, CA); Cho, Jin (Palo Alto, CA); Kye, Jongwook (Pleasanton, CA), filed on January 6, 2012, was published online on July 1, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8765599 is assigned to GlobalFoundries, Inc. (Grand Cayman, KY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices, decreasing transistors size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing industry. As the size and spacing of the transistors decrease, it is more difficult to avoid inadvertent creation of electrical connections between adjacent devices, which, in turn, reduces yield."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A method is provided for fabricating a semiconductor device structure. The semiconductor device includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure. The method involves forming a first layer of a first dielectric material overlying the doped region, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and the gate structure, and forming a second conductive contact electrically connected to the gate structure within the second layer.

"In another embodiment, a method of fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, removing portions of the first layer to form a first voided region overlying the doped region. forming a first conductive contact electrically connected to the doped region in the first voided region, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure formed on the semiconductor substrate, removing portions of the second layer overlying the gate structure to form a second voided region exposing the gate structure while leaving the dielectric cap intact, and forming a second conductive contact electrically connected to the gate structure in the second voided region.

"In yet another embodiment, an apparatus for a semiconductor device is provided. The semiconductor device structure includes a substrate of a semiconductor material, a gate structure overlying the substrate, a doped region formed in the substrate proximate the gate structure, a first dielectric material overlying the doped region, a first conductive contact electrically connected to the doped region formed in the first dielectric material, and a dielectric cap overlying the first conductive contact.

"This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter."

URL and more information on this patent, see: Yuan, Lei; Cho, Jin; Kye, Jongwook. Semiconductor Devices Having Dielectric Caps on Contacts and Related Fabrication Methods. U.S. Patent Number 8765599, filed January 6, 2012, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765599.PN.&OS=PN/8765599RS=PN/8765599

Keywords for this news article include: Electronics, Semiconductor, GlobalFoundries Inc..

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Source: Electronics Newsweekly


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