News Column

Patent Issued for Replicating a Driver of a Net in a Circuit Design

July 15, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- Xilinx, Inc. (San Jose, CA) has been issued patent number 8769461, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Li, Yau-Tsun S. (San Jose, CA); Sultania, Anup K. (Sunnyvale, CA); Reddy, E. Syama Sundara (Secunderabad, IN).

This patent was filed on January 15, 2013 and was published online on July 1, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.

"Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

"The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.

"The process of implementing a circuit design within a particular integrated circuit (IC), referred to as a target device, typically begins with an architecture description of the circuit design. This description can be specified in a hardware description language (HDL) such as Verilog or VHDL. Most circuit designs have one or more timing requirements that must be observed. The timing requirements can be expressed within the programmatic description of the circuit design or as supplemental information or files accompanying the circuit design.

"Electronic Design Automation (EDA) tools can process the circuit design and find an implementation for a given target device that meets the timing requirements. The EDA tool typically converts the HDL description of the circuit design into a gate-level representation of the circuit design. With respect to programmable logic device (PLD) type ICs, such as field programmable gate arrays, the gate level description can be technology mapped to vendor specific structures available within the target device. Elements of the circuit design are assigned to different components of the target device, e.g., lookup tables, flip-flops, and the like.

"After technology mapping, delay information for interconnects of the circuit design can be calculated. The delay information for interconnects is effectively an estimation of signal propagation delays within the circuit. Because the circuit design has not yet been placed, this estimation of interconnect delays generally is not considered highly accurate.

"The EDA tool then can place the technology mapped circuit design. The various elements of the circuit design, now associated with components of the target device, can be assigned to pre-fabricated sites, or locations, of the target device. The placement task generally can be guided by the delay information available. Connections of the circuit design can be routed to generate a routed circuit design.

"Conventional EDA tools often have difficulty in processing signals of the circuit design that are distributed to a large number of load pins. It is often the case that these 'high fanout signals' (HF signals or HF nets) contribute to the failure of the EDA tool to determine a satisfactory implementation of the circuit design, e.g., an implementation that conforms to the established timing requirements."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "A method of processing a circuit design for implementation on a target device is provided in one embodiment. For a first driver that is a driver of a net having a plurality of loads, a second driver that is a driver of the first driver is selected. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. Connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

"In another embodiment, a circuit is provided for processing a circuit design for implementation on a target device. The circuit includes at least one processor and a memory arrangement coupled to the at least one processor. The memory arrangement is configured with instructions for causing the at least one processor to perform operations including, for a first driver that is a driver of a net having a plurality of loads, selecting a second driver that is a driver of the first driver. A representation of a rectilinear Steiner arborescence (RSA) tree is generated from the second driver and the plurality of loads. The RSA tree includes nodes representative of the plurality of loads and a plurality of Steiner points. A subset of the plurality of Steiner points in the RSA tree is selected for disposing respective replicated instances of the first driver. The respective replicated instances of the first driver are assigned to locations on the target device associated with the subset of Steiner points. Connections from each of the respective replicated instances of the first driver are assigned to a respective subset of the plurality of loads.

"Other embodiments will be recognized from consideration of the Detailed Description and Claims, which follow."

For the URL and additional information on this patent, see: Li, Yau-Tsun S.; Sultania, Anup K.; Reddy, E. Syama Sundara. Replicating a Driver of a Net in a Circuit Design. U.S. Patent Number 8769461, filed January 15, 2013, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8769461.PN.&OS=PN/8769461RS=PN/8769461

Keywords for this news article include: Technology, Xilinx Inc.

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Source: Journal of Technology


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