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Patent Issued for Replacement Gate CMOS

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Cheng, Kangguo (Guilderland, NY); Yang, Haining S. (Wappingers Falls, NY), filed on March 22, 2012, was published online on July 1, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8765558 is assigned to International Business Machines Corporation (Armonk, NY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The invention relates generally to complementary metal oxide semiconductor (CMOS) structures, and methods for fabricating CMOS structures. More particularly, the invention relates to CMOS structures with enhanced performance, and methods for fabricating those CMOS structures.

"In addition to stand alone transistors (i.e., including field effect transistors (FETs), as well as bipolar transistors), resistors, diodes and capacitors, semiconductor structures also often include CMOS structures. A CMOS structure includes a complementary doped pair of field effect transistor devices including a pFET device and an nFET device. CMOS structures and CMOS devices are desirable within the semiconductor fabrication art insofar as semiconductor circuit configurations that are based upon CMOS structures and CMOS devices provide for reduced power consumption in comparison with alternative semiconductor circuit configurations that are not based upon CMOS structures and CMOS devices.

"In addition, CMOS structures and CMOS devices have been successfully scaled in dimension for several decades to provide for continued enhancements in semiconductor circuit performance and semiconductor circuit functionality.

"While CMOS structures and CMOS devices are quite common in the semiconductor fabrication art, similarly with other semiconductor structures and semiconductor devices they are not entirely without limitations.

"In that regard, as CMOS structure and CMOS device dimensions continue in a scaled decrease, lithographic limitations for uniformly fabricating individual pFET and nFET components (i.e., such as but not limited to gates) with desirable resolution and dimensional control within a particular CMOS structure becomes increasingly more challenging."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "The invention provides a CMOS structure and a method for fabricating the CMOS structure. The CMOS structure includes a first gate located over a first active region of a first polarity within a semiconductor substrate and a second gate located over a second active region of a second polarity different than the first polarity within the semiconductor substrate. The first gate and the second gate are co-linear, and facing endwalls of the first gate and the second gate (i.e., that are separated by a gap) terminate over an isolation region that separates the first active region and the second active region. The facing endwalls of the first gate and the second gate do not have a spacer located and formed adjacent or adjoining thereto. In comparison, nominally parallel and co-linear sidewalls of the first gate and the second gate do have a spacer located adjacent or adjoining thereto. In addition, separating the facing endwalls of the first gate and the second gate over the isolation region is a vertical portion of a multi-planar 'T' shaped dielectric layer.

"Within the context of the invention as disclosed and claimed, a 'multi-planar `T` shaped' dielectric layer is intended as comprising a 'T' shape with respect to any of several vertical planes that pass through the vertical portion of the 'T.'

"The CMOS structure in accordance with the invention may be fabricated using a sequential replacement gate methodology that provides the gap between the first gate and the second gate. This particular gap is filled with the vertical portion of the multi-planar T shaped dielectric layer. The particular methodology in accordance with the invention provides that the first gate and the second gate may be fabricated with superior dimensional control by using the replacement gate methodology, rather than a lithographic and etch methodology.

"A particular CMOS structure in accordance with the invention includes a first FET having a first polarity and including a first gate located upon a first gate dielectric located upon a first active region of a semiconductor substrate. This particular CMOS structure also includes a second FET having a second polarity different than the first polarity and including a second gate located upon a second gate dielectric located upon a second active region of the semiconductor substrate separated from the first active region of the semiconductor substrate by an isolation region. The first gate and the second gate are co-linear. An endwall of the first gate and an endwall of the second gate terminate facing each other over the isolation region absent a spacer located adjacent or adjoining the facing endwall of the first gate or the facing endwall of the second gate, but including a spacer adjacent or adjoining a sidewall of the first gate and a sidewall of the second gate.

"Another particular CMOS structure in accordance with the invention includes a first FET having a first polarity and including a first gate located upon a first gate dielectric located upon a first active region of a semiconductor substrate. This other particular CMOS structure also includes a second FET having a second polarity different than the first polarity and including a second gate located upon a second gate dielectric located upon a second active region of the semiconductor substrate separated from the first active region of the semiconductor substrate by an isolation region. The first gate and the second gate are co-linear. An endwall of the first gate and an endwall of the second gate terminate facing each other over the isolation region and are separated by a gap, absent a spacer adjacent or adjoining the facing endwall of the first gate or the facing endwall of the second gate, but including a spacer adjacent or adjoining a sidewall of the first gate and a sidewall of the second gate. This other particular CMOS structure also includes a multi-planar T shaped passivation layer passivating the first FET and the second FET, and filling the gap.

"A particular method for fabricating a CMOS structure in accordance with the invention includes forming over a semiconductor substrate that includes a first active region of a first polarity separated from a second active region of a second polarity different polarity than the first polarity by an isolation region a dummy CMOS structure that includes a dummy gate that traverses the first active region, the isolation region and the second active region. This particular method also includes removing a first portion of the dummy gate over the first active region and an adjoining portion of the isolation region to provide a first aperture, and backfilling the first aperture with a first gate. This particular method also includes removing a second portion of the dummy gate over the second active region and an adjoining portion of the isolation region to provide a second aperture, and backfilling the second aperture with a second gate that is separated from the first gate by a third remainder portion of the dummy gate. This particular method also includes removing the third remainder portion of the dummy gate to provide a third aperture bounded by facing endwalls of the first gate and the second gate. This particular method also includes filling the third aperture with a passivation layer."

URL and more information on this patent, see: Cheng, Kangguo; Yang, Haining S.. Replacement Gate CMOS. U.S. Patent Number 8765558, filed March 22, 2012, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765558.PN.&OS=PN/8765558RS=PN/8765558

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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