News Column

Patent Issued for Programmable Cache Access Protocol to Optimize Power Consumption and Performance

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Delgross, Joseph (Chandler, AZ); Jamil, Sujat (Gilbert, AZ); O'Bleness, R. Frank (Tempe, AZ); Hameenanttila, Tom (Phoenix, AZ); Miner, David E. (Chandler, AZ), filed on June 4, 2013, was published online on July 1, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8769204 is assigned to Marvell International Ltd. (Hamilton, BM).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Cache memory is used by processing units to reduce the average time to access memory, i.e., stored instructions and/or data, and thereby avoid processing delays, or latency, due to the processor waiting on the receipt of required instructions and/or data. Cache memory can be accessed more quickly than main memory or external memory stores due to its closer physical proximity to the CPU and a configuration that is designed for fast access with reduced overhead. Therefore by moving blocks of data from main memory, or external memory to cache memory, prior to use, the majority of CPU memory accesses may be faster cache memory accesses, thereby allowing the CPU to process data and instructions at frequencies closer to the designed operational frequency of the CPU."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A programmable cache and cache access protocol is described that can be dynamically optimized with respect to either power consumption or performance, i.e., speed of response, based on a monitored performance of the cache. A cache controller dynamically configures the cache to operate in either a serial processing mode, for optimized power consumption, or a parallel processing mode, for optimized performance. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and dynamically reconfigures the programmable cache to operate in parallel mode if the monitored performance parameters exceed a maximum threshold in order to increase cache performance at the cost of greater power consumption. Further, the monitoring unit can dynamically reconfigure the programmable cache to operate in serial mode if the monitored performance parameters are at or below a predetermined threshold, in order to conserve power at the cost of potential performance.

"A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy is also described. An array structure that requires unaligned access, e.g., such as an instruction cache, can be organized into banks, e.g., an even bank for the low-order word of an aligned access, and an odd bank for the high order word. Each bank can hold a portion of the complete data required, e.g., in an instruction cache, each bank can hold one of two instructions stored within a cache access that is stored across the two banks. The banks can then be independently addressed. In cases where an unaligned access is desired, the address to the odd bank can be incremented. For example, for the unaligned access case, multiplexers can be used to swap the data from each bank to assemble the final quantity. Often these multiplexers can be an extension of other multiplexers already present in a typical design, e.g., such as source selection multiplexers. The approach allows for aligned and unaligned data accesses and therefore increased cycle performance with minimal impact to frequency performance.

"A cache access controller with prefetch capability is also described. Typically the size of the lowest-level cache in a microprocessor has a direct impact on the frequency performance and cycle performance of the microprocessor. To achieve fast frequency performance, the cache can be made small, yet a small cache could have a cycle performance impact due to lower hit rate. One solution to this issue is to have multi-levels of cache, e.g., in which the closest level can be made smaller if there is a larger cache behind it to offset the low-hit rate of the smaller cache. However there may still be cycle performance degradation if the lowest level cache consistently needs to get data from the next level. An approach is described for addressing such a condition by providing a mechanism by which data can be prefetched from an outer level of a cache to the inner level. More specifically, the described mechanism performs such prefetching without incurring a hardware structural hazard related to the translation lookaside buffer (TLB) structure.

"In one example embodiment a programmable cache is described that includes, a tag array unit that forwards either a delayed wayhit result or a non-delayed wayhit result based on a configurable control parameter, a data array unit that generates either a single data array cache line or multiple data array cache lines based on the configurable control parameter, and a cache controller that configures the tag array unit and the data array unit to operate in either in parallel or in series based on the configurable control parameter.

"In a second example embodiment, a programmable cache is described that includes, a tag array unit that forwards either a delayed wayhit result or a non-delayed wayhit result based on a configurable control parameter, a data array unit that generates either a single data array cache line or multiple data array cache lines based on the configurable control parameter, and a cache controller that configures the tag array unit and the data array unit to operate in either parallel or in series based on the configurable control parameter. The tag array unit can further include, an N-way tag array that includes N tag arrays, and a wayhit comparator that initiates a search of the N-way tag array based on a received request tag and compares results received from the N tag arrays to produce a wayhit result, which indicates which of the tag arrays contains data matching the request tag.

"In a third example embodiment, a method of controlling a programmable cache is described that may include, forwarding either a delayed wayhit result or a non-delayed wayhit result based on a configurable control parameter, generating either a single data array cache line or multiple data array cache lines based on the configurable control parameter, and configuring a tag array unit and a data array unit to operate in either in parallel or in series based on the configurable control parameter."

URL and more information on this patent, see: Delgross, Joseph; Jamil, Sujat; O'Bleness, R. Frank; Hameenanttila, Tom; Miner, David E.. Programmable Cache Access Protocol to Optimize Power Consumption and Performance. U.S. Patent Number 8769204, filed June 4, 2013, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8769204.PN.&OS=PN/8769204RS=PN/8769204

Keywords for this news article include: Electronics, Microprocessors, Marvell International Ltd..

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Source: Electronics Newsweekly


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