News Column

Patent Issued for Power Module Having Stacked Flip-Chip and Method of Fabricating the Power Module

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Lim, Seung-won (Bucheon-si, KR); Jeon, O-Seob (Seoul, KR); Son, Joon-seo (Seoul, KR); Lee, Keun-kyuk (Bucheon-si, KR); Choi, Yun-hwa (Incheon, KR), filed on December 21, 2009, was published online on July 1, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8766419 is assigned to Fairchild Korea Semiconductor, Ltd. (Wonmi-District, Bucheon, Kyonggi Province, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments of the present invention relate to a semiconductor package and a method of fabricating the same, and more particularly, to a stack type power module and a method of fabricating the same.

"In general, when a semiconductor package is fabricated, a semiconductor chip or a plurality of semiconductor chips is mounted on a lead frame or a printed circuit board (PCB), and sealed for protection reasons using a sealant, e.g., an epoxy molding compound (EMC). The semiconductor package is mounted on a mother board or a system PCB.

"In line with requirements for high speed, large storage capacity, and high integration of electronic devices, demands for compact, light, and inexpensive power devices have increased. To satisfy such demands, a plurality of semiconductor chips is mounted in a semiconductor package to constitute a stack type power module. However, in such a stack type power module, chips are generally connected to a lead frame or the like using wire bonding. Thus, the possibilities to reduce the size of the stack type power module are limited.

"FIG. 1 is a cross-sectional view of a conventional power module package disclosed in Korean Patent Publication Gazette No. 2002-0095053, entitled 'Power Module Package Having Improved Heat Emission Capability and Method of Fabricating the Same.' Referring to FIG. 1, the conventional power module package has a structure in which a plurality of power device chips 22 and a plurality of control device chips 30 are mounted on a lead frame 40 and sealed using a sealant 50. The lead frame 40 is divided into portions A and B, which are different from each other and in which the power device chips 22 and the control device chips 30 are respectively mounted. In other words, a thermal substrate 10 is disposed under the portion A of the lead frame 40 to emit heat generated from the power device chips 22. The thermal substrate 10 is attached to the portion A of the lead frame 40 through a solder paste 12.

"In the conventional power module package, the power device chips 22 or the control device chips 30 are mounted on the lead frame 40 through metal wires 24 formed of Au or Al using a bonding method. Thus, a space for wire bonding must be secured. Thus, the possibility to reduce the size of the conventional power module package is limited. Also, since wire bonding is used, the wires may be cut or an operation characteristic of the conventional power module package may be deteriorated due to a long length of the wires.

"FIG. 2 is a cross sectional view of another conventional power module package disclosed in U.S. Pat. No. 5,703,399, entitled 'Semiconductor Power Module.' Referring to FIG. 2, the conventional power module package has a structure in which a plurality of power device chips 5a and a plurality of control device chips 4a are mounted on a lead frame 3, and a thermal substrate 1 is disposed under the lead frame 3. A sealant for sealing the power device chips 5a and the control device chips 4a is divided into upper and lower sealants 7 and 2. The lower sealant 2 is formed of a highly thermal conductive material. A resistive component 5b is disposed on the left side of the power device chips 5a, and the conventional power module package is divided into portions A and B in which the power device chips 5a and the control device chips 4a are respectively mounted. Here, 6A and 6B are metal wires.

"In the conventional power module package of FIG. 2, the power device chips 5a and the control device chips 4a are mounted on the lead frame 3 using wire bonding as described above. Thus, like in the case of the conventional power module package of FIG. 1, the possibility to reduce the size of the conventional power module package of FIG. 2 is limited. Also, since the upper and lower sealants 7 and 2 are formed of different materials, a sealing process is complicated. Since the lower sealant 2 emits heat, the conventional power module package is disadvantageous in view of the material and thickness of the lower sealant 2."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "The present invention provides a stack type power module having reduced size and improved operational characteristics due to the reduced size and a method of fabricating the stack type power module.

"According to an aspect of the present invention, there is provided a power module having a stacked flip-chip, including a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

"The power module may further include a thermal substrate which emits heat generated from the power device part. A copper (Cu) thin film may be stacked on a ceramic substrate to form the thermal substrate.

"The lead frame may include first and second lead frame portions, the first lead frame portion may have a long portion extends underneath the interconnecting substrate and the second lead frame portion that may have a short portion that extends on (e.g., on top of) the interconnecting substrate, the power device part may be disposed between the first lead frame portion and the thermal substrate, and the power device chip of the power device part may be attached to a lower surface of the first lead frame portion using a flip-chip bonding method. The first lead frame portion may be divided into lower and upper portions to have a predetermined bending depth, and the lower portion of the first lead frame portion may long extend underneath the interconnecting substrate. A convex type bump may be formed on the lower portion of the first lead frame portion to combine the first lead frame portion with the power device chip. Upper and lower boards may be attached to each other to form the interconnecting substrate, and predetermined patterns may be formed on the lower board of the interconnecting substrate so as to dispose the first lead frame portion among the predetermined patterns.

"The power device chip of the power device part may be adhered onto the thermal substrate through a solder adhesive of solder wire or solder paste type. The control device chip of the control device part may be attached to an upper surface of the interconnecting substrate using a flip-chip bonding method. The power and control device chips may be attached to one of the interconnecting substrate and the first lead frame portion using one of a bump structure, a solder structure, and a bump and solder structure.

"The power and control device chips may be attached to one of the interconnecting substrate and the first lead frame portion using one of the bump and solder structure and the solder structure, and one of the bump and solder structure and the solder structure may include a structure which includes one of a bump which is formed on a pad of the chips and a solder material which encloses the bump and is formed between the chip and one of the interconnecting substrate and the first lead frame portion; a first bump which is formed on the pad of the chip, a second bump which is formed on one of the interconnecting substrate and the first lead frame portion, and a solder material which encloses the first and second bumps and is formed between the chip and one of the interconnecting substrate and the first lead frame portion; a stack type bump which is formed on the pad of the chip and a solder material which encloses the stack type bump and is formed between the chip and one of the interconnecting substrate and the first lead frame portion; a stack type bump which is formed on one of the interconnecting substrate and the first lead frame portion and a solder material which encloses the stack type bump and is formed between the chip and one of the interconnecting substrate and the first lead frame portion; a solder material which is formed between the pad of the chip and one of the interconnecting substrate and the first lead frame portion; and a bump which is formed on one of the interconnecting substrate and the first lead frame portion and a solder material which encloses the bump and is formed on the chip and one of the interconnecting substrate and the first lead frame portion. The bump may be formed of one of copper (Cu) and gold (Au) in a convex structure, and if the bump is of stack type, the bumps may include two bumps including protrusions which are attached to each other so that they face each other or away from each other.

"The power and control device chips may be attached to one of the interconnecting substrate and the first lead frame portion using a bump structure, and the bump structure may include a structure which includes one of a first bump which is formed on a pad of the chip and a second bump which is connected to the first bump and formed on one of the interconnecting substrate and the first lead frame portion; a first bump which is formed on the pad of the chip, one of plate-shaped aluminum (Al) bump and pattern which is formed on one of the interconnecting substrate and the first lead frame portion, and a second bump which is formed between the first bump and one of the plate-shaped Al bump and pattern; a first bump which is formed on the pad of the chip and a tin (Sn) plated plate which is connected to the first bump and formed on one of the interconnecting substrate and the first lead frame portion; and a first bump which is formed on the pad of the chip, a second bump which is formed on the first bump, and a Sn plated plate which is connected to the second bump and formed on one of the interconnecting substrate and the first lead frame portion. The first and second bumps may be formed of one of Cu and Au in convex structures and may include protrusions which are attached to each other so that they face toward or away from each other. An under bump metal (UBM) may be formed on the pad of the chip.

"The lead frame may operate as a thermal substrate, and the power device chip of the power device part may be disposed between the interconnecting substrate and the lead frame. The power device chip of the power device part may be adhered onto the lead frame through a solder adhesive of solder wire or solder paste type and may be attached to a lower surface of the interconnecting substrate using a flip-chip bonding method. The lead frame may be connected to the interconnecting substrate through inter-substrate solder balls. The control device chip of the control device part may be attached to an upper surface of the interconnecting substrate using a flip-chip bonding method. The power module may further include a sealant which seals the power and control device parts and may include a convex structure including a predetermined portion protruding from a lower portion of the lead frame.

"According to another aspect of the present invention, there is provided a power module having a stacked flip-chip, including a control device part including a control device chip; a power device part including a power device chip; a thermal substrate on which the power device part is attached and which emits heat generated from the power device part; a lead frame which is disposed on the thermal substrate and attached to the power device chip of the power device part using a flip-chip bonding method; and an interconnecting substrate which is attached to the lead frame and on which the control device chip of the control device part is stacked using a flip-chip bonding method.

"The lead frame may include first and second lead frame portions, the first lead frame portion may have a long portion that extends underneath the interconnecting substrate, and the second lead frame portion may have a short portion that extends on the interconnecting substrate. Upper and lower boards may be attached to each other to form the interconnecting substrate, and predetermined patterns may be formed on the lower board of the interconnecting substrate so as to dispose the first lead frame portion among the predetermined patterns. The first lead frame portion may be divided into lower and upper portions to have a predetermined bending depth, and the lower portion of the first lead frame portion may have a long portion that extends underneath the interconnecting substrate.

"The control device part may include one of a boost diode (B.S diode) and a thermistor, and the power device part may include a diode chip. The control device chip may include low and high voltage integrated circuits (LV and HV ICs), and the power device chip may include an IGBT (insulated gate bipolar transistor) chip. The power module may have a DIP (dual in-line package) structure.

"According to another aspect of the present invention, there is provided a power module having a stacked flip-chip, including a control device part including a control device chip; a power device part including a power device chip; a lead frame on which the power device part is stacked; and an interconnecting substrate which is disposed on the lead frame and of which the power device chip of the power device part and the control device chip of the control device part are respectively disposed at upper and lower portions using a flip-chip bonding method.

"The lead frame may operate as a thermal substrate and may be connected to the interconnecting substrate through inter-substrate solder balls. The power module may further include a sealant which seals the power and control device parts and has a convex structure including a predetermined portion protruding from a lower portion of the lead frame. The power device chip may include a MOSFET (metal-oxide semiconductor field effect transistor).

"The power module may have an SMD (surface mount device) package structure.

"According to another aspect of the present invention, there is provided a method of fabricating a power module, including forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a thermal substrate and the control device chip onto an interconnecting substrate; combining a lead frame, the thermal substrate, and the interconnecting substrate with one another in a multi jig (or other suitable type of processing apparatus); and sealing the power and control device chips, and the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.

"The bumps may be formed on the lead frame and the interconnecting substrate. The method may further include performing a reflow process between the combining of the lead frame, the thermal substrate, and the interconnecting substrate and the sealing of the power and control device chips; plating a predetermined portion of the lead frame outside the sealant after sealing the power and control device chips; trimming the predetermined portion of the lead frame; and performing test and packing processes. The reflow process may include a flux cleaning process.

"The lead frame may include first and second lead frame portions. The first lead frame portion may have a long portion that extends underneath the interconnecting substrate and the second lead frame portion may have a short portion that extends on the interconnecting substrate, the power device part may be disposed between the first lead frame portion and the thermal substrate, and the power device chip of the power device part may be attached to a lower surface of the first lead frame portion using a flip-chip bonding method.

"The power device chips may be adhered onto the thermal substrate using a solder screen print process, and the control device chips may be adhered onto the interconnecting substrate using solder balls, or a solder paste dotting or dispense, or thermal press process. The combination of the lead frame, the thermal substrate, and the interconnecting substrate may be performed using solder paste dotting or solder screen print processes.

"According to another aspect of the present invention, there is provided a method of fabricating a power module, including forming bumps on power and control device chips on a wafer level; separately sawing the power and control device chips into individual chips; adhering the power device chip onto a lead frame and the control device chip onto an interconnecting substrate; combining the lead frame with the interconnecting substrate in a multi-jig; and sealing the power and control device chips; and the control and power device chips may be respectively attached to the interconnecting substrate and the lead frame using a flip-chip bonding method.

"The lead frame may operate as a thermal substrate, and the power device chip of the power device part may be disposed on the lead frame and underneath the interconnecting substrate using a flip-chip bonding method. A sealant may be formed underneath the lead frame so that a predetermined portion of the sealant protrudes so as to fabricate the power module in a convex structure."

URL and more information on this patent, see: Lim, Seung-won; Jeon, O-Seob; Son, Joon-seo; Lee, Keun-kyuk; Choi, Yun-hwa. Power Module Having Stacked Flip-Chip and Method of Fabricating the Power Module. U.S. Patent Number 8766419, filed December 21, 2009, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8766419.PN.&OS=PN/8766419RS=PN/8766419

Keywords for this news article include: Electronics, Fairchild Korea Semiconductor Ltd..

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Source: Electronics Newsweekly


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