News Column

Patent Issued for Parasitic Extraction in an Integrated Circuit with Multi-Patterning Requirements

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Buck, Nathan (Underhill, VT); Dreibelbis, Brian (Underhill, VT); Dubuque, John P. (Jericho, VT); Foreman, Eric A. (Fairfax, VT); Habitz, Peter A. (Hinesburg, VT); Hathaway, David J. (Underhill, VT); Hemmett, Jeffrey G. (Bolton Valley, VT); Venkateswaran, Natesan (Hopewell Junction, NY); Visweswariah, Chandramouli (Croton-on-Hudson, NY); Zolotov, Vladimir (Putnam Valley, NY), filed on October 31, 2012, was published online on July 1, 2014.

The assignee for this patent, patent number 8769452, is International Business Machines Corporation (Armonk, NY).

Reporters obtained the following quote from the background information supplied by the inventors: "An IC is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect its electronic and circuit components.

"Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. IC design layouts typically include circuit modules (e.g., geometric representations of electronic or circuit IC components) with pins, and interconnect lines (e.g., geometric representations of wiring) that connect the pins of the circuit modules. A net is typically defined as a collection of pins that need to be connected. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create the design layouts, design engineers typically use electronic design automation ('EDA') applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts.

"A process traditionally performed in the design of the IC is called parasitic extraction. Parasitic extraction is the calculation of parasitic effects (e.g., parasitic capacitances, parasitic resistances and parasitic inductances) in both the designed electronic components and the required wiring interconnects of the IC. The purpose of the parasitic extraction is to create an accurate analog model of the circuit, such that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as timing analysis, circuit simulation, and signal integrity analysis. Analog circuits are often run in detailed test benches to indicate if the extracted parasitics may allow the designed IC to function within predetermined specifications.

"The manufacturing requirements at advanced process nodes, such as multi-patterning lithography at 0.02 .mu.m, are advancing newer parasitic modeling techniques to achieve signoff accuracy and performance. Multi-patterning lithography is an important technique for ensuring printability of device and interconnect layers in advanced process node manufacturing. However, splitting layers into multiple masks can introduce timing variations because of mask misalignment in the manufacturing process. For example, the misalignment of the layout masks may cause variations in coupling capacitances between the polygons that are on different masks, which in turn affects both the couplings and the total capacitances of the nets.

"Errors introduced into the parasitic extraction by multi-patterning depend on mask displacement amount. Impact on coupling capacitance can be large, even while it is smaller on total capacitance, due to the different impact on coupling capacitances at the opposite sides of conductor segments. To enable successful advanced process node manufacturing, a multi-patterning aware modeling solution for parasitic extraction is needed to account for the timing impact and to address the multi-patterning in the physical implementation and signoff design flow.

"Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In a first aspect of the invention, a method of parasitic extraction is provided for multi-patterning in an integrated circuit design. The method includes determining resistance solutions and capacitance solutions for a netlist of the integrated circuit design using a processor. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.

"In another aspect of the invention, a method of parasitic extraction is provided for multi-patterning in an integrated circuit design. The method includes determining resistance solutions and capacitance solutions for a netlist of the integrated circuit design using a processor. The method further includes performing a first parasitic extraction of the resistance solutions and the capacitance solutions to generate a first set of parasitic values comprising mean values for the resistance solutions and the capacitance solutions. The method further includes modifying at least one geometrical value to a new value for each vector of parameters identified within the integrated circuit design based on a shift in value attributable to multi-patterning for a given layer of the integrated circuit design. The method further includes performing a second parasitic extraction of the resistance solution and the capacitance solution based on the modified at least one geometrical value, to generate a second set of parasitic values. The method further includes determining a difference between the first set of parasitic values and the second set of parasitic values to generate sensitivities. The method further includes generating as output statistical parasitics in at least one of a vector form and a collapsed reduced vector form using a processor.

"In yet another aspect of the invention, a computer program product is provided comprising a computer readable storage medium having readable program code embodied in the storage medium. The computer program product includes at least one component operable to determine resistance solutions and capacitance solutions for a netlist of an integrated circuit design. The at least one component is further operable to perform a first parasitic extraction of the resistance solutions and the capacitance solutions to generate a first set of parasitic values comprising mean values for the resistance solutions and the capacitance solutions. The at least one component is further operable to identify a separate parameter for each pattern or color of multi-patterning for a given layer of the integrated circuit design, wherein the parameter for each pattern or color of the multi-patterning is a vector of parameters. The at least one component is further operable to modify at least one geometrical value to a new value for each vector of parameters identified within the integrated circuit design based on a shift in value attributable to the multi-patterning for the given layer of the integrated circuit design. The at least one component is further operable to perform a second parasitic extraction of the resistance solution and the capacitance solution based on the modified at least one geometrical value, to generate a second set of parasitic values. The at least one component is further operable to determine a difference between the first set of parasitic values and the second set of parasitic values to generate sensitivities. The at least one component is further operable to generate as output statistical parasitics in at least one of a vector form and a collapsed reduced vector form."

For more information, see this patent: Buck, Nathan; Dreibelbis, Brian; Dubuque, John P.; Foreman, Eric A.; Habitz, Peter A.; Hathaway, David J.; Hemmett, Jeffrey G.; Venkateswaran, Natesan; Visweswariah, Chandramouli; Zolotov, Vladimir. Parasitic Extraction in an Integrated Circuit with Multi-Patterning Requirements. U.S. Patent Number 8769452, filed October 31, 2012, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8769452.PN.&OS=PN/8769452RS=PN/8769452

Keywords for this news article include: Electronic Components, International Business Machines Corporation.

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Source: Electronics Newsweekly


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