The patent's assignee for patent number 8766332 is
News editors obtained the following quote from the background information supplied by the inventors: "In traditional circuit layout for a semiconductor die, features are arranged most densely in the substrate and at the same or lower density in subsequent wiring layers formed above the substrate. Pitch (the center-to-center distance between features of an integrated circuit) generally has been relaxed in higher layers due to the difficulty of accurately patterning and etching features over a surface which is not perfectly planar. Topography and deviations from planarity tend to increase in higher layers. Moreover, for simplicity of layout, it is usual to make shorter connections in lower wiring layers, and longer connections in higher wiring layers. As wiring is longer in higher layers, slowing device speed, it has been seen to be advantageous to increase the width and thickness of the wiring to lower its resistance, which has also tended to increase pitch at higher layers.
"It has become increasingly important to increase device density, fitting more devices into a smaller substrate area. Increased pitch in higher layers has generally been acceptable, as the device density has been limited by feature density in the substrate, and not by the pitch of above-substrate wiring.
"If, however, devices are formed entirely above the substrate, pitch of above-substrate layers becomes more important. Smaller pitch increases lithography costs, however, increasing overall device cost. There is a need, therefore, for above-substrate pitch to be minimized while minimizing overall cost."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a method for optimizing pitch and critical dimensions of features in and above a substrate in semiconductor devices.
"A first aspect of the invention provides for a semiconductor die comprising a substrate device level having a substrate pitch, and a first above-substrate device level formed above the substrate device level, the first above-substrate device level having a first above-substrate pitch, wherein the first above-substrate pitch is smaller than the substrate pitch.
"A related aspect of the invention provides for a semiconductor die comprising a substrate device level having a substrate pitch, and a first memory level above a substrate having a first memory pitch, wherein the first memory pitch is smaller than the substrate pitch.
"Another aspect of the invention provides for a monolithic three dimensional memory array comprising a substrate device level comprising devices formed in a substrate having a first pitch, and a first memory level formed over the substrate device having a second pitch, wherein the second pitch is smaller than the first pitch.
"A preferred embodiment of the invention provides for a semiconductor die comprising a first device level formed in a substrate, the first device level having a first pitch, and a first plurality of substantially parallel, substantially coplanar rails formed above the substrate, the first plurality of rails having a second pitch, wherein the first pitch is larger than the second pitch.
"An additional aspect of the invention provides for a semiconductor device level comprising a first area comprising a plurality of substantially parallel, substantially coplanar rails, the first plurality of rails having a first pitch, and a second area having a second pitch, wherein the second pitch is larger than the first pitch, wherein photolithographic techniques optimized for forming rails are used to pattern the semiconductor device level.
"A preferred embodiment of the invention provides for a semiconductor die comprising a substrate device level having a substrate critical dimension, and a first above-substrate device level formed above the substrate device level, the first above-substrate device level having a first above-substrate critical dimension, wherein the first above-substrate critical dimension is smaller than the substrate critical dimension.
"Each of the aspects and embodiments of the invention can be used alone or in combination with one another.
"The preferred embodiments will now be described with reference to the attached drawings."
For additional information on this patent, see: Cleeves, James M.; Scheuerlein, Roy E.. Optimization of Critical Dimensions and Pitch of Patterned Features in and above a Substrate. U.S. Patent Number 8766332, filed
Keywords for this news article include: Electronics, Semiconductor,
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