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Patent Issued for Nonvolatile Memory Array Having Modified Channel Region Interface

July 15, 2014



By a News Reporter-Staff News Editor at Journal of Technology -- A patent by the inventor Liao, Yi Ying (Sijhih, TW), filed on May 18, 2010, was published online on July 1, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8765553 is assigned to Macronix International Co., Ltd. (Hsinchu, TW).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The technology relates to nonvolatile memory, and in particular, nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

"Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names PHINES, SONOS, or NROM, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.

"Conventional nonvolatile nitride cell structures are planar, such that the oxide-nitride-oxide (ONO) structure is formed on the surface of the substrate. However, such planar structures are associated with poor scalability, high power program and erase operations, and a high sheet resistance. Such a structure is described in YEH, C. C., et al., 'PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,' Electron Devices Meeting, 2002. IEDM '02. Digest. International, 8-11 Dec. 2002, Pages: 931-934.

"Accordingly, it would be desirable to modify the planar structure of conventional nonvolatile nitride cell structures, to address one or more of these shortcomings."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "One aspect of the technology is a nonvolatile memory cell integrated circuit, comprising a nonvolatile memory array.

"The nonvolatile memory array includes multiple columns, each including multiple nonvolatile memory cells arranged in a series. A subset of nonvolatile memory cells in the series are electrically connected to a bit line via other nonvolatile memory cells in the series. An example is the NAND arrangement.

"Each nonvolatile memory cell of the array includes a charge storage structure, source and drain regions, and one or more dielectric structures. The charge storage structure stores charge to control a logical state stored by the nonvolatile memory cell integrated circuit. In various embodiments, the charge storage structure stores one bit or multiple bits. In various embodiments, the material of the charge storage structure is a charge trapping structure or a nanocrystal structure. The source and drain regions are separated by a channel region, which is part of the circuit that undergoes inversion to electrically connect the source and drain regions. The dielectric structures electrically isolate parts of the circuit from each other, in the absence of an electrical field to overcome the dielectric structures. The dielectric structures are at least partly between the charge storage structure and the channel region and at least partly between the charge storage structure and a source of gate voltage.

"For each nonvolatile memory cell of the array, an interface separates part of the one or more dielectric structures from the channel region. A first end of the interface ends at an intermediate part of the source region and a second end of the interface ends at an intermediate part of the drain region. To implement the interface, in one embodiment the channel region is recessed into a substrate of the nonvolatile memory cell integrated circuit.

"Some embodiments include a gate length scaling dielectric layer at least partly between a substrate and the dielectric structures.

"Another aspect of the technology is a method of making a nonvolatile memory cell array integrated circuit, comprising:

"forming columns of nonvolatile memory cells in the array, each including nonvolatile memory cells arranged in a series. An example is the NAND arrangement. This step includes the following: forming a charge storage structure and one or more dielectric structures for each nonvolatile memory cell in the array. The charge storage structure stores charge to control a logical state stored by the nonvolatile memory cell integrated circuit. In various embodiments, the charge storage structure stores one bit or multiple bits. In various embodiments, the material of the charge storage structure is a charge trapping structure or a nanocrystal structure. The dielectric structures are 1) at least partly between the charge storage structure and a channel region and 2) at least partly between the charge storage structure and a source of gate voltage. forming a conductive layer providing the gate voltage.

"forming bit lines providing drain voltage and source voltage to each column of nonvolatile memory cells in the array, such that a subset of nonvolatile memory cells in each column are electrically connected to a bit line via other nonvolatile memory cells in the series;

"For each nonvolatile memory cell of the array, an interface separates part of the one or more dielectric structures from the channel region. A first end of the interface ends at an intermediate part of the first bit line and a second end of the interface ends at an intermediate part of the second bit line. To implement the interface, one embodiment forms a recess in a substrate, such that charge trapping structure and dielectric structures are formed in the recess.

"Some embodiments scale gate length by forming a liner at least partly between the dielectric structures and a substrate. Some embodiments, prior to forming the charge storage structure and the dielectric structures, include: scaling gate length by forming a dielectric layer and removing parts of the dielectric layer.

"Another aspect of the technology is a method of making a nonvolatile memory cell array integrated circuit, comprising:

"forming a charge storage structure and one or more dielectric structures for each nonvolatile memory cell in the array. The charge storage structure stores charge to control a logical state stored by the nonvolatile memory cell integrated circuit. In various embodiments, the charge storage structure stores one bit or multiple bits. In various embodiments, the material of the charge storage structure is a charge trapping structure or a nanocrystal structure. The one or more dielectric structures are 1) at least partly between the charge storage structure and a channel region and 2) at least partly between the charge storage structure and a source of gate voltage.

"forming a first part of the conductive layer providing the gate voltage.

"after forming the first part of the conductive layer providing the gate voltage, forming bit lines providing drain voltage and source voltage to each nonvolatile memory cell in the array, such as by adding dopants. The channel region of each nonvolatile memory cell in the array extends between a first bit line of the bit lines providing the drain voltage and a second bit line of the bit lines providing the source voltage. An example is the NOR arrangement.

"after forming the bit lines, forming a second part of the conductive layer providing the gate voltage. The first part and the second part of the conductive layer are physically connected. Some embodiments include, forming a dielectric layer separating the bit lines from the second part of the conductive layer.

"For each nonvolatile memory cell of the array, an interface separates part of the one or more dielectric structures from the channel region. A first end of the interface ends at an intermediate part of the first bit line and a second end of the interface ends at an intermediate part of the second bit line. To implement the interface, one embodiment forms a recess in a substrate, such that charge trapping structure and dielectric structures are formed in the recess.

"Some embodiments scale gate length by forming a liner at least partly between the one or more dielectric structures and a substrate. Some embodiments, prior to forming the charge storage structure and the dielectric structures, include: scaling gate length by forming a dielectric layer and removing parts of the dielectric layer.

"In other embodiments of the technology, the dielectric structure between at least partly between the charge trapping structure and the channel region, includes an ONO structure as disclosed herein."

URL and more information on this patent, see: Liao, Yi Ying. Nonvolatile Memory Array Having Modified Channel Region Interface. U.S. Patent Number 8765553, filed May 18, 2010, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765553.PN.&OS=PN/8765553RS=PN/8765553

Keywords for this news article include: Technology, Macronix International Co. Ltd..

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Source: Journal of Technology


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