News Column

Patent Issued for Methods of Forming Variable Resistive Memory Devices

July 16, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Kang, Myung Jin (Yongin-si, KR), filed on June 13, 2012, was published online on July 1, 2014.

The patent's assignee for patent number 8765564 is Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR).

News editors obtained the following quote from the background information supplied by the inventors: "Embodiments relate to methods of forming semiconductor devices and, more particularly, to methods of forming variable resistive memory devices.

"Semiconductor devices can be, e.g., semiconductor memory devices and semiconductor logic devices. The semiconductor memory devices may store data. The semiconductor memory devices may be categorized as, e.g., volatile memory device and nonvolatile memory devices. Volatile memory devices may lose their stored data when their power supply is interrupted. Nonvolatile memory devices may retain their stored data even when their power supply is interrupted. The nonvolatile memory devices may include, e.g., programmable read only memory (PROM) devices, erasable PROM (EPROM) devices, electrical EPROM (EEPROM) devices and flash memory devices.

"Semiconductor memory devices may also include, for example, ferroelectric random access memory (FRAM) devices, magnetic random access memory (MRAM) devices and phase-change random access memory (PRAM) devices. Memory cells may include a variable resistive material, which may have a characteristic that the electrical resistance of the material varies according to current or voltage applied thereto. Further, when included as part of a memory cell, the variable resistive material may retain its final electrical resistance even though the current and/or voltage supply is interrupted."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Embodiments are directed to forming variable resistive memory devices.

"Embodiments may be realized by a method that includes forming a conductive pattern and a first insulation pattern on a substrate, such that the conductive pattern alternates with the first insulation pattern along a first direction on a substrate, the first direction being parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern, such that the preliminary sacrificial pattern contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch mask, thereby forming a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern, such that at least two portions of the sacrificial pattern are separated from each other along a second direction intersecting the first direction, and at least two portions of the bottom electrode pattern are separated from each other along the second direction, and replacing the sacrificial pattern with a variable resistive pattern.

"In an embodiment, the method may further include forming a second insulation pattern covering a sidewall of the preliminary sacrificial pattern prior to formation of the preliminary bottom electrode pattern, wherein etching the conductive pattern may include using the second insulation pattern as an etch mask together with the preliminary sacrificial pattern.

"In an embodiment, the method may further include forming top electrode pattern on the variable resistive pattern.

"In an embodiment, a sidewall of the conductive pattern may be in contact with a sidewall of the first insulation pattern, and a top surface of the first insulation pattern may be located above a top surface of the conductive pattern.

"In an embodiment, the method may further include forming an interlayer insulation pattern between the substrate and the conductive pattern, such that the interlayer insulation pattern includes openings that expose a portion of the substrate, and selection elements may be formed in the respective openings.

"In an embodiment, the selection elements may be arrayed in at least two columns that are parallel with the second direction when viewed from a plan view, and forming the conductive pattern may include forming portions of the conductive pattern such that each of the portions of the conductive pattern at least partially overlaps a first selection element and a second selection element, the first and second selection elements being from respective first and second columns of the at least two columns.

"In an embodiment, forming the conductive pattern and the first insulation pattern may include forming a conductive layer on the substrate including the selection elements, forming a third insulation pattern on the conductive layer, such that the third insulation pattern extends along the second direction, patterning the conductive layer using the third insulation pattern as an etch mask to form the conductive pattern, forming the first insulation pattern between portions of the third insulation pattern and removing the third insulation pattern to form a trench that exposes the conductive pattern.

"In an embodiment, the method may further include forming an ohmic pattern in the respective openings, such that the ohmic pattern is between the respective selection elements and the conductive pattern.

"In an embodiment, etching the conductive pattern to form a preliminary bottom electrode pattern may include at least partially etching an upper portion of the ohmic pattern and an upper portion of the interlayer insulation layer.

"In an embodiment, the third insulation pattern may be formed of a material having an etch selectivity with respect to the first insulation pattern.

"In an embodiment, after forming the preliminary bottom electrode pattern, the trench may extend into a region between two portions of the preliminary bottom electrode pattern, and a fourth insulation pattern may be formed that fills the trench.

"In an embodiment, forming the fourth insulation patterns may include exposing the preliminary sacrificial pattern using a planarization process.

"In an embodiment, the sacrificial pattern may be formed of a material having an etch selectivity with respect to the first, second and fourth insulation pattern.

"In an embodiment, forming the conductive layer may include sequentially forming first and second conductive layers on the substrate having the selection elements, and the second conductive layer may be formed of a material having a resistivity greater than a resistivity of the first conductive layer.

"In an embodiment, the preliminary sacrificial patterns may be formed to contact the sidewall of the first insulation pattern using a spacer formation process.

"In an embodiment, etching the conductive pattern may include etching the portions of the conductive pattern such that each of the portions of the conductive pattern is formed into at least two portions of the preliminary bottom electrode pattern.

"Embodiments may be realized by a method that includes forming a first insulation pattern on a substrate, such that the first insulation pattern includes portions on either side of a trench, forming a preliminary sacrificial pattern, such that a portion of the preliminary sacrificial pattern is in the trench and contacts a sidewall of at least one of the portions of the first insulation pattern, and replacing the sacrificial pattern with a variable resistive pattern.

"In an embodiment, the preliminary sacrificial pattern may be formed such that a first sidewall of the portion of the preliminary sacrificial pattern contacts a sidewall of at least one of the portions of the first insulation pattern, and a second sidewall of the portion of the preliminary sacrificial pattern may be exposed, the second sidewall being opposite the first sidewall.

"In an embodiment, the method may further include forming a conductive pattern on the substrate prior to forming the preliminary sacrificial pattern, and etching the conductive pattern using the preliminary sacrificial pattern as an etch mask, thereby forming a preliminary bottom electrode pattern.

"In an embodiment, the method may further include forming a second insulation pattern covering the second sidewall of the portion of the preliminary sacrificial pattern prior to formation of the preliminary bottom electrode pattern, wherein etching the conductive pattern may include using the second insulation pattern as an etch mask together with the preliminary sacrificial pattern."

For additional information on this patent, see: Kang, Myung Jin. Methods of Forming Variable Resistive Memory Devices. U.S. Patent Number 8765564, filed June 13, 2012, and published online on July 1, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8765564.PN.&OS=PN/8765564RS=PN/8765564

Keywords for this news article include: Semiconductor, Random Access Memory, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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