Patent number 8766281 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This invention relates to a light emitting diode chip, which has small package volume and which can be rapidly manufactured, and methods for manufacturing and packaging the light emitting diode chip.
"As shown in FIG. 1, a conventional light emitting diode chip 91 is electrically connected to external electrodes 93 on a substrate 92 by a wire bonding process. However, a larger space on the substrate 92 is required for the wire bonding process. In addition, since wire connections are made one by one using a machine during the wire bonding process, the production efficiency is relatively low and is unfavorable for a system in package or a wafer level package.
"In order to alleviate the problems attributed to the wire bonding process, a flip chip process is commonly used for replacing the wire bonding process. However, in the flip chip process, there is a need to deposit plenty of gold bumps on each chip, which is time-consuming and also decreases the packaging process efficiency of the chip. Aside from the flip chip process, other packaging methods without using the wire bonding process are also proposed. For example, the chip can be flipped such that the electrodes on the chip are directly mounted onto the electrodes on the substrate without providing the gold bumps therebetween. However, in packaging method, those electrodes on the chip should be formed equally in height to have an excellent flatness. Therefore, the precision requirement for the electrodes is relatively high, and it is relatively difficult to manufacture the chips for such packaging method. Furthermore, another packaging method by modifying the structure of the chip has been proposed heretofore. According to this method, the electrodes of the chip extend from a top surface of the chip to a bottom surface thereof. For example, a method of making a chip disclosed in JP 2008-130875, as shown in FIGS. 2 and 3, includes: forming a via hole 941 in a chip 94, followed by forming a conductive layer 95 for electrically connecting an electrode 96 on a top surface of the chip 94 to an electrode 97 on a bottom surface of the chip 94. Therefore, the electrode 97 of the chip 94 can be provided on the bottom surface of the chip 94. However, in the case of JP 2008-130875, the via hole 941 defines a vertical via-hole sidewall. When forming the conductive layer 95 along the vertical via-hole sidewall, it is likely to result in a poor step coverage (non-uniform surface coverage) of the via-hole sidewall and a poor conductivity of the conductive layers."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "In order to solve the above-mentioned problems, a light emitting diode chip, methods for making and packaging the light emitting diode chip, a package structure of the light emitting diode, and a method for making a reflective cup used for packaging the light emitting diode chip are provided in the present invention.
"According to the present invention, alight emitting diode chip is provided with two inclined sidewalls on two sides thereof. Due to the inclined sidewalls, it is easy to deposit the conductive portions evenly on the inclined sidewalls, thereby avoiding a problem of poor step coverage. Furthermore, with the conductive layers on the inclined sidewalls connections of the electrodes of the light emitting diode chip can be extended to two sides or the bottom side of the substrate. Such an arrangement facilitates subsequent packaging processes of the light emitting diode chip. Particularly, no wire bonding process is needed in this invention, and the package volume of the light emitting diode chip can be reduced.
"The invention further provides methods of forming a reflective cup and packaging the light emitting diode for system in package or wafer level package. It merely requires one step photolithography process to form a cavity with a reflection layer. Compared to the prior art which requires two steps of photolithography, this invention reduces processing time and production cost. Furthermore, the packaging method of the invention does not need any wire bonding process to form a wiring connection with the package substrate, thereby saving the processing time, enhancing productivity, and reducing the package volume.
"The invention further provides a packaging method in which connections of the electrodes on the light emitting diode chip can be extended to the lower surface of the package substrate without forming a via hole inside the reflective cup, thereby avoiding destruction to the sealing of the light emitting diode chip, and eliminating the problems of the prior art in that the chip is susceptible to moisture and the package structure is likely to be fragile due to the via hole in the reflective cup used for extending the electrode to a bottom of the package substrate. In addition, the package structure produced by the invention can be directly mounted on a printed circuit board of an application product without using the wire bonding process. Accordingly, the yield of defective products due to wire breakage can be reduced, the reliability of the package structure can be improved, and assembling of the package structure will be more simplified and more convenient for downstream application processes.
"In the light emitting diode chip of the invention, by virtue of the inclined plane units, the conductive portions connected to the electrodes can be extended to the substrate inclined walls or the bottom surface of the substrate, and electrical connections can be formed directly by mounting the light emitting diode chip on the package substrate or by forming the conductive extension portions using a metallization process. Since there is no need to conduct the wire bonding process, it facilitates the utilization of the light emitting diode chip in a system in package or wafer level package, saves the time for wire bonding, and saves the space for wire bonding to reduce the packaging volume. Besides, the light emitting diode chip is advantageous to miniaturize other photoelectric devices, and is more flexible for integration with other LED technologies, such as nano-crystal coating process. In addition, by forming the inclined sidewalls and the substrate inclined walls and by depositing the conductive portion on the inclined faces thereof, it is easier to control the deposition on the inclined faces, compared to the vertical via-hole sidewall in the prior art. Thus, a yield rate of the light emitting diode chip can be improved, and the cost thereof can be reduced.
"In the method for making a reflective cup according to this invention, by protruding the portion of the protection portion adjacent to the cavity, the metal layer formed in the cavity does not extend out of the opening of the cavity, thereby eliminating one photolithography step and saving the processing time and production costs.
"In the method for packaging the light emitting diode provided in this invention, the plurality of light emitting diode chips can be packaged on the same package substrate without using the wire bonding process. Thus, the packaging method is suitable for use in a system in package or wafer level package. Based on the package structure of the light emitting diode, a proper method for packaging can be selected such that the conductive portions connected to the electrodes of the light emitting diode chip can be extended out of the opening of the reflective cup, or be extended to the lower surface of the package substrate. Therefore, the light emitting diode chip can be provided with a perfect sealing. By such packaging method, not only can the processing time and the packaging volume be reduced, it is also convenient for the assembling processes in downstream applications."
URL and more information on this patent, see: Kao, Chih-Chiang. Light Emitting Diode Chip, and Methods for
Keywords for this news article include: Photolithography,
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