The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "Embodiments in the present disclosure generally relate to improved memory architectures. More particular, embodiments relate to implementation of logic, e.g., combinational or sequential logic, connected with a memory on either a common die or connected dice, such that, the logic can process data in the memory and avoid transferring the data outside the memory die or connected set of logic and memory dice.
"As technology improves, the speed of data processing has increased at an exponential rate. With the improvements have come consumer expectations that applications running on computers would improve at a similar rate.
"As processing speed has continued to improve, bottlenecks are becoming apparent in the memory related areas of computer design. For example, latency in accessing memory has become a significant issue in current computer design. Many improvements have been explored in an attempt to address this issue. For example, multiple levels of cache have been used to provide faster access to memory based on how often or recent data has been accessed. For example, some current systems have three levels of cache and a main memory (RAM) in addition to the traditional hard drive disk used to store memory. In such example systems, the first level of cache may only require 4 cycles to access but may only be able to store 64K bytes of data. The second level may require 10 cycles to access, but may be able to store 512K bytes of data. The third level may require 40 cycles to access, but may be able to store 2 MB of data. Random Access Memory (RAM) can store an additional 4-8 GB of data, for example, but may take 6000 cycles to access. But all of these memory components are faster than a hard drive, which may store 100s of GBs of data, but may take 10s or 100s of thousands of cycles to access."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventor's summary information for this patent application: "Therefore, data processing system performance may be increased by executing common memory intensive processes without requiring the transfer of contents (data) between the memory integrated circuit and a separate processing unit.
"An embodiment includes a memory integrated circuit designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. In an embodiment, the logic component can include combinational or sequential logic.
"Another embodiment includes a central processing unit (CPU) and a system memory integrated circuit, coupled to the CPU, designed to execute a task on the data in a memory array within the system memory integrated circuit. The system memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. In an embodiment, the logic component can include combinational or sequential logic.
"Another embodiment includes a method for processing data within a memory integrated circuit. The method includes determining the memory address, retrieving data from a memory array located at the memory address, executing a task using the data to produce a result, and returning the result if the result satisfies an exit condition.
"Further features and advantages of the invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art based on the teachings contained herein.
BRIEF DESCRIPTION OF THE DRAWINGS
"The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate some embodiments and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art to make and use the invention.
"FIG. 1 is a block diagram of an exemplary memory system of an improved memory architecture with attached logic, all in a single integrated circuit according to an embodiment.
"FIG. 2 is a flowchart of an exemplary method performed by an incorporated memory architecture with attached logic, such as that shown in FIG. 1, according to an embodiment.
"FIGS. 3A and 3B collectively illustrate is a block diagram of an exemplary memory system with dedicated search hardware, all in an integrated circuit, according to an embodiment.
"FIG. 4 is a flowchart of an exemplary search method performed by dedicated search hardware, such as shown in FIGS. 3A and 3B, according to an embodiment.
"The features and advantages of embodiments of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number."
For more information, see this patent application: McClain, Mark A. Memory Device with Internal Combination Logic. Filed
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