News Column

Patent Application Titled "Fabrication Method of Packaging Substrate" Published Online

July 18, 2014



By a News Reporter-Staff News Editor at Health & Medicine Week -- According to news reporting originating from Washington, D.C., by NewsRx journalists, a patent application by the inventors Yen, Lee-Sheng (Toayuan, TW); Wang, Doau-Tzu (Taoyuan, TW), filed on February 26, 2014, was made available online on July 3, 2014 (see also Advance Materials Corporation).

The assignee for this patent application is Advance Materials Corporation.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to packaging substrates and fabrication methods thereof, and more particularly, to a packaging substrate which facilitates thinning of package structures and a fabrication method thereof.

"Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high performance. To minimize semiconductor packages, packaging substrates carrying semiconductor chips are required to have reduced thicknesses. Such a packaging substrate can be made of a hard material or a soft material. Packaging substrates used in ball grid array (BGA) packages are generally made of a hard material.

"FIGS. 1A to 1C are schematic cross-sectional views showing a fabrication method of a packaging substrate 1 having double-layer circuits.

"Referring to FIG. 1A, a core layer 10 is provided. The core layer 10 has a first surface 10a having a first metal layer 11a disposed thereon, a second surface 10b opposite to the first surface 10a and having a second metal layer 11b disposed thereon, and a plurality of through holes 100 penetrating the first and second surfaces 10a, 10b.

"Referring to FIG. 1B, a patterning process is performed to use the first and second metal layers 11a, 11b (using a conductive layer 12 on the first and second metal layers 11a, 11b as a current conductive path for electroplating) to form a first circuit layer 13a and a second circuit layer 13b on the first surface 10a and the second surface 10b of the core layer 10, respectively, and form a plurality of conductive through holes 14 in the through holes 100 for electrically connecting the first and second circuit layers 13a, 13b. Therein, the first and second circuit layers 13a, 13b have a plurality of first and second conductive pads 130a, 130b, respectively.

"Referring to FIG. 1C, a first insulating protection layer 15a and a second insulating protection layer 15b are formed on the first surface 10a and the second surface 10b of the core layer 10, respectively. The first and second insulating protection layers 15a, 15b have a plurality of first and second openings 150a, 150b for exposing the first and second conductive pads 130a, 130b, respectively. Further, a first surface finish layer 16a and a second surface finish layer 16b are formed on the exposed first and second conductive pads 150a, 150b, respectively.

"Subsequently, a semiconductor chip can be disposed on the second insulating protection layer 15b and encapsulated by an encapsulant so as to form a package structure. According to the current processing technology, the thickness S of the packaging substrate 1 can be reduced to 150 um.

"However, such a packaging substrate having a thickness of 150 um is difficult to meet the miniaturization requirement of semiconductor packages. On the other hand, if the thickness of the packaging substrate 1 is reduced to be less than 150 um, the packaging substrate 1 is easy to crack during transportation or packaging, thereby adversely affecting the product yield.

"Therefore, there is a need to provide a packaging substrate and a fabrication method thereof so as to overcome the above-described drawbacks."

In addition to obtaining background information on this patent application, NewsRx editors also obtained the inventors' summary information for this patent application: "Accordingly, the present invention provides a packaging substrate, which comprises: a core layer having a first surface and a second surface opposite to the first surface; a first circuit layer formed on the first surface of the core layer and having a plurality of first conductive pads; a second circuit layer formed on the second surface of the core layer and having a plurality of second conductive pads; a plurality of conductive through holes penetrating the core layer for electrically connecting the first and second circuit layers; a first insulating protection layer disposed on the first surface of the core layer and the first circuit layer and having a plurality of openings for exposing the first conductive pads of the first circuit layer, respectively; a first surface finish layer formed on the exposed first conductive pads; a second insulating protection layer formed on the second surface of the core layer and the second circuit layer and having a plurality of openings for exposing the second conductive pads of the second circuit layer, respectively; a second surface finish layer formed on the exposed second conductive pads; and a carrier attached to the first insulating protection layer through an adhesive layer.

"The present invention further provides a fabrication method of a packaging substrate, which comprises the steps of: providing two core layers each having a first surface having a first metal layer formed thereon and a second surface opposite to the first surface and having a second metal layer formed thereon, and a plurality of through holes penetrating through the first metal layer and the first surface of the core layer so as to expose portions of the second metal layer; bonding the second metal layers of the two core layers together through an adhesive member for connecting the two core layers; using the first metal layer of each of the core layers to form a first circuit layer having a plurality of first conductive pads on the first surface of the core layer and form conductive through holes in the through holes of the core layer for electrically connecting the first circuit layer; forming first insulating protection layers on the first surfaces of the core layers and the first circuit layers, each of the first insulating protection layers having a plurality of openings for exposing the first conductive pads so as for a first surface finish layer to be formed on the exposed first conductive pads; attaching a carrier to each of the first insulating protection layers through an adhesive layer; removing the adhesive member so as to obtain two substrate bodies; stacking the carriers of the two substrate bodies on one another by using a bonding member so as to expose the second metal layers; using the second metal layer of each of the core layers to form a second circuit layer having a plurality of second conductive pads and electrically connecting the conductive through holes; forming second insulating protection layers on the second surfaces of the core layers and the second circuit layers, each of the second insulating protection layers having a plurality of openings for exposing the second conductive pads so as for a second surface finish layer to be formed on the exposed second conductive pads, thereby forming two packaging substrates; and removing the bonding member so as to separate the two packaging substrates from each other.

"The present invention further provides another fabrication method of a packaging substrate, which comprises the steps of: providing two core layers each having a first surface having a first metal layer formed thereon and a second surface opposite to the first surface and having a second metal layer formed thereon, and a plurality of through holes penetrating through the first metal layer and the first surface of the core layer so as to expose portions of the second metal layer; bonding the second metal layers of the two core layers together through an adhesive member for connecting the two core layers; using the first metal layer of each of the core layers to form a first circuit layer having a plurality of first conductive pads on the first surface of the core layer and form conductive through holes in the through holes of the core layer for electrically connecting the first circuit layer; forming first insulating protection layers on the first surfaces of the core layers and the first circuit layers, each of the first insulating protection layers having a plurality of openings for exposing the first conductive pads so as for a first surface finish layer to be formed on the exposed first conductive pads; attaching a carrier to each of the first insulating protection layers through an adhesive layer; removing the adhesive member so as to obtain two substrate bodies; using the second metal layer of each of the substrate bodies to form a second circuit layer having a plurality of second conductive pads and electrically connecting the conductive through holes; and forming a second insulating protection layer on the second surface of the core layer and the second circuit layer, the second insulating protection layer having a plurality of openings for exposing the second conductive pads so as for a second surface finish layer to be formed on the exposed second conductive pads.

"Therein, the adhesive layers can be made of glue or release agent, and the carriers can be made of a high temperature resistant material.

"Further, the thickness of the packaging substrate minus the thickness of the carrier thereof is less than 150 um.

"Therefore, by attaching a carrier to the first insulating protection layer of the packaging substrate, the packaging substrate is prevented from cracking during transportation or packaging. Furthermore, after the carrier is removed, the packaging substrate has a thickness less than 150 um, which accordingly leads to a package structure having a reduced thickness. Therefore, the packaging substrate of the present invention meets the requirements of both miniaturization and reliability.

BRIEF DESCRIPTION OF DRAWINGS

"FIGS. 1A to 1C are schematic cross-sectional views showing a conventional fabrication method of a packaging substrate having double-layer circuits;

"FIGS. 2A to 2I are schematic cross-sectional views showing a fabrication method of a packaging substrate according to an embodiment of the present invention, wherein FIG. 2F' shows another embodiment of FIG. 2F; and

"FIGS. 3A to 3C are schematic cross-sectional views showing a fabrication method of a packaging substrate according to another embodiment of the present invention."

For more information, see this patent application: Yen, Lee-Sheng; Wang, Doau-Tzu. Fabrication Method of Packaging Substrate. Filed February 26, 2014 and posted July 3, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=7393&p=148&f=G&l=50&d=PG01&S1=20140626.PD.&OS=PD/20140626&RS=PD/20140626

Keywords for this news article include: Electronics, Semiconductor, Microtechnology, Advance Materials Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Health & Medicine Week


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters