The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "System-on-a-chip or system on chip (also named after the acronyms SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). An integrated circuit or monolithic integrated circuit (also referred to as IC, chip, and microchip) is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material. It may contain digital, analog, mixed-signal, and often radio-frequency functions--all on a single chip substrate. A typical application is in the area of embedded systems.
"In current System on Chip, the different components are interconnected by an on-chip interconnect. An interconnect can basically be construed as a bus for circuitry. Examples of such interconnect are Open Core Protocol (also named after its acronym OCP) or Advanced RISC Machines.RTM.'s (also named after its acronym ARM) Advanced eXtensible Interface (also named after its acronym AXI). The components may be Control Processor Units (also named after their acronym CPU). ARM A9 processor core is an example of CPU. Direct memory access (also named after its acronym DMA) engines or peripherals such as Universal Asynchronous Receivers Transmitters (also named by its acronym UARTs) may also be considered as components.
"Each component is usually memory mapped. Furthermore, the components exchange transactions between each other.
"Such transactions comprise a request sent to another component, wherein this request is executed. As illustrations, the request may be an instruction to read, to write or to fetch from memory. The component that sends the request is a transactions initiator component or initiator component whereas the component that executes the request is a transactions target component or target component. Some components are capable of being both a transactions initiator and a transactions target, while others may be only be a transaction initiator or a transaction target.
"Each transaction that is initiated shall have a response that contains either the information requested or status of the original request. As examples, the information requested may be read data while the status may be successful or failed write indications. The response is sent by the target component to the component which initiated the transaction.
"In addition to transactions that are sent on the on-chip bus, components also exchange status information such as interrupts. As interrupts are usually side-band signals, on-chip interconnects therefore also contain side-band signals.
"Sometimes, all the functionalities needed in a SoC cannot be implemented efficiently in a single die. In such cases, the SoC is split into multiple, usually two. For instance, some components contain analog modules that are designed in a different technology process node while other components are purely digital and can be designed in a smaller process node.
"Low Latency Interface (also named after its acronym LLI) may be used to enable such flexible partitioning of a SoC or a system into multiple physical dies while the software implemented in the system considers them as a single logical die. The LLI is standardized in Mobile Industry Processor Interface (also named after its acronym MIPI). LLI is a point to point interface that allows two dies to communicate as if the other die was located on the die considered. LLI is a bi-directional interface made up of dual-simplex sub-links. LLI allows both dies to initiate and to receive transactions simultaneously. In other words, LLI can be thought of as a 'bus-extension' or 'interconnect tunnel'. Through special transactions called 'Service transactions', LLI can carry the side-band signals such as interrupts.
"In order to efficiently manage the LLI physical link power supply, it is possible to power down the link or put the link into very low power supply states. The physical link requires time to be active when starting from a low power supply state. Such time is usually in the range of milliseconds. As 'interconnect tunnel' protocols such as LLI should be able to ensure the low latency while transporting the transactions, it is desirable that all outstanding transactions are completed before the link is put in such low power consumption states or in the extreme case, powered down."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The object of the present invention is to alleviate at least partly the above mentioned drawbacks.
"More particularly, the invention aims to power down the link between two ICs or put the link into very low power supply states in a secure way.
"This object is achieved with a method for controlling transaction exchanges between two integrated circuits in a system comprising the two integrated circuits and a power supply for powering a link between the two integrated circuits, thereby enabling transaction exchanges between both integrated circuits. The system also comprises a controller controlling the integrated circuits and the power supply. This can generally be referred to as a link management system. In LLI terminology one chip is called a 'System Master' as it will be controlling the LLI IPs (on both chips) and also manage the link. The System Master is equivalent to the controller 40. In FIG. 1, 'controller' item 40 points to both ICs for generality. Typically, though, only the master has a controller. In that case, the slave 'controller' manages e.g. clock, power and reset in the slave. The master controller 40 could also control the slave by issuing orders to the slave PMU. Once done, the slave PMU reports back to the master PMU.
"The method comprises the step of a) receiving an order at the controller to lower an amount of power supplied by the power supply to the link and a step c) of lowering the power supplied to the link once any pending transactions have been executed. In between, there may be a step b) of sending an instruction from the controller to both integrated circuits to prevent the integrated circuits from initiating new transactions.
"Embodiments may comprise one or more of the following features: the order is an order to power down the link. the link is a circuit-to-circuit serial interface protocol (thus also applicable to parallel interfaces, as they comprise serial connections). the link is a MIPI Low Latency Interface at least one of the integrated circuits has an interconnect supplied by an interconnect power supply, which is only used in the transaction exchanges between the two integrated circuits and step c further comprises lowering the power supplied by the interconnect power supply once any pending transactions have been executed. one integrated circuit is a master integrated circuit and the other integrated circuit is a slave integrated circuit. the system comprises at least one monitor able to provide a signal representative of a number of pending transactions, the method further comprising a step between step b) and step c) of sending the signal from the monitor to the controller when the number of pending transactions reaches zero.
"It is also proposed a system comprising two integrated circuits, a power supply for powering a link between the two integrated circuits, thereby enabling transaction exchanges between both integrated circuits. It is also proposed a controller for controlling the integrated circuits and the power supply. The controller is adapted to send an instruction to both integrated circuits to prevent the integrated circuits from initiating new transactions when receiving an order to lower an amount of power supplied by the power supply to the link and to lower the power supplied to the link once any pending transactions have been executed.
"Preferred embodiments comprise one or more of the following features: the controller is adapted to send an instruction to both integrated circuits to prevent the integrated circuits from initiating new transactions when receiving an order to power down the link and to stop the supply power of the link once any pending transactions have been executed. the controller is adapted to send an instruction to both integrated circuits to prevent the integrated circuits from initiating new transactions when receiving an order to power down the link. the controller is adapted to act as the controller in at least one of the method as previously described.
"Further features and advantages of the invention will appear from the following description of embodiments of the invention, given as non-limiting examples, with reference to the accompanying drawings listed hereunder.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 shows a block diagram of an example of a system partitioned into two separate ICs,
"FIG. 2 shows a flowchart of a method for controlling transaction exchanges between the two ICs and in the system,
"FIGS. 3 and 4 are schematic flowcharts of an example of method used to reliably know that there are no pending transactions initiated either from an IC or the other."
For additional information on this patent application, see: Balakrishnan, Bipin; Goulahsen, Abdelaziz. Method for Controlling Transaction Exchanges between Two Integrated Circuits. Filed
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