The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "The embodiments of the present invention relate to processing systems that have two or more processors, such as two or more processor cores, and particularly relate to those processing systems in which one of the processors or processor cores can be executing instructions or otherwise operating while another processor or processor core can be in a low power state such as a low power sleep state in which processing is reduced or totally eliminated.
"A common chain of events in modem computing operating systems can start with a hardware interrupt that causes a first processor to wake up (from a low power sleep state) and execute an interrupt handler. This in turn causes a thread to be made runnable to which the scheduler responds by executing that thread. In multi-processor systems, the operating system must make choices about when to wake up additional processors, particularly when the first processor receives a new interrupt while it is already processing an interrupt and while a second processor is in a low power sleep state. If the first processor chooses not to wake up the second (or other additional) processors, then the execution of the newly runnable thread will be delayed while the first processor continues processing any interrupts. This adds scheduling latency to the newly runnable thread, but potentially avoids waking up the second processor that may have nothing to do. Most of the time this added latency is short, but in a busy system, additional interrupts could delay the thread significantly. If the operating system chooses to wake up the second processor or additional processor as soon as the thread is made runnable, the thread will see minimal scheduling latency. However, if the interrupt processing on the first processor completes quickly, the original processor (the first processor) will then he left with nothing to do and be put back to sleep. In effect, two processors would be woken up to do one processor's amount of work. Both of these strategies are used in modern operating systems, depending on the expected workload and desired balance between performance and power efficiency."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "A multi-processor system uses, in one embodiment, a deferred inter-processor interrupt (IPI) that is issued by a first processor. The deferred IPI can be cancelled, and if it is not cancelled it wakes up a second processor. The deferred IPI is issued by the first processor in response to a new interrupt that is, in one embodiment, received while the first processor is processing a previously received interrupt. If the first processor can complete processing of the previously received interrupt before a timer, started by the deferred IPI, times out, then the first processor can handle the new interrupt and can cancel the deferred IPI.
"In one embodiment, a method to process interrupts in a multi-processor system which includes at least a first processor and a second processor and an interrupt controller that is coupled to both processors, can include: receiving at the first processor, from the interrupt controller, a first interrupt and processing the first interrupt with an interrupt handler that is executing on the first processor while the second processor is in a low power sleep state, the processing of the first interrupt creating a runnable thread or otherwise making a thread runnable; requesting, by the first processor in response to the creation of the runnable thread, a deferred inter-processor interrupt (IPI) by sending a deferred IPI to the interrupt controller; starting a timer in the interrupt controller in response to the deferred IPI; and cancelling the deferred IPI in response to determining, before the timer in the interrupt controller times out. that the first processor is available to execute the runnable thread, the cancelling including sending a cancel signal, to cancel the deferred IPI, from the first processor to the interrupt controller. In the event that the timer does time out, the method can also include waking up the second processor from the low power sleep state in response to the timer timing out and also assigning the runnable thread to the second processor for processing on the second processor. In one embodiment, the interrupt handler executing in the first processor cannot be interrupted but a thread in cither of the first processor or the second processor can be interrupted. In one embodiment, a scheduler software component in the operating system which is executing on the first processor requests the deferred IPI. Also in one embodiment, the deferred IPI can specify a time value (or a value which is representative of time) to be used by the timer in the interrupt controller to set a timeout period. In another embodiment, the interrupt controller can provide its own time value and does not require a time value or a time representative value from the processor. In one embodiment, the first processor processes the runnable thread alter cancelling the deferred IPI. In one embodiment, the multiple processor system has no priority scheme for interrupts. In one embodiment, the first processor cancels the deferred IPI by sending a cancel indicator or cancel signal to the interrupt controller which changes the value in a cancel register of the interrupt controller, thereby preventing the deferred IPI from being sent by the interrupt controller to the other processor. In one embodiment, the interrupt controller can include a plurality of registers to store indicators or parameters for a deferred IPI, such as an indicator that indicates a deferred IPI is to be sent when a corresponding timer expires unless a cancel indicator has been stored in a cancel register.
"The embodiments described herein also include systems which perform one or more of the methods described herein and also include machine readable non-transitory storage media that store executable program instructions which, when executed by a data processing system having at least two processors, cause the data processing system to perform any one of the methods described herein.
"The above summary does not include an exhaustive list of all embodiments. It is contemplated that the invention includes all systems and methods that can be practiced from all suitable combinations of the various aspects summarized above, and also those disclosed in the Detailed Description below.
BRIEF DESCRIPTION OF THE DRAWINGS
"The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.
"FIG. 1 shows an example of a data processing system which can be used in one or more embodiments.
"FIG. 2 shows an example of a data processing system that includes an interrupt controller that can provide a deferred inter-processor interrupt.
"FIG. 3 is a flowchart which shows a method according to one embodiment.
"FIG. 4 shows an embodiment of an interrupt controller that can provide a deferred inter-processor interrupt.
"FIG. 5 shows an example of a data processing system that can be used in one or more embodiments."
For additional information on this patent application, see: Kumar, Derek R.;
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