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Researchers Submit Patent Application, "Accelerated Recovery for Snooped Addresses in a Coherent Attached Processor Proxy", for Approval

August 5, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Blaner, Bartholomew (Underhill Center, VT); Cummings, David W. (Round Rock, TX); Daly, JR., George W. (Ausstin, TX); Siegel, Michael S. (Raleigh, NC); Stuecheli, Jeff A. (Austin, TX), filed on September 25, 2013, was made available online on July 24, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to data processing, and more specifically, to a coherent proxy for an attached processor.

"A conventional distributed shared memory computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.

"Because multiple processor cores may request write access to a same memory block (e.g., cache line or sector) and because cached memory blocks that are modified are not immediately synchronized with system memory, the cache hierarchies of multiprocessor computer systems typically implement a cache coherency protocol to ensure at least a minimum required level of coherence among the various processor core's 'views' of the contents of system memory. The minimum required level of coherence is determined by the selected memory consistency model, which defines rules for the apparent ordering and visibility of updates to the distributed shared memory. In all memory consistency models in the continuum between weak consistency models and strong consistency models, cache coherency requires, at a minimum, that after a processing unit accesses a copy of a memory block and subsequently accesses an updated copy of the memory block, the processing unit cannot again access the old ('stale') copy of the memory block.

"A cache coherency protocol typically defines a set of cache states stored in association with cached copies of memory blocks, as well as the events triggering transitions between the cache states and the cache states to which transitions are made. Coherency protocols can generally be classified as directory-based or snoop-based protocols. In directory-based protocols, a common central directory maintains coherence by controlling accesses to memory blocks by the caches and by updating or invalidating copies of the memory blocks held in the various caches. Snoop-based protocols, on the other hand, implement a distributed design paradigm in which each cache maintains a private directory of its contents, monitors ('snoops') the system interconnect for memory access requests targeting memory blocks held in the cache, and responds to the memory access requests by updating its private directory, and if required, by transmitting coherency message(s) and/or its copy of the memory block.

"The cache states of the coherency protocol can include, for example, those of the well-known MESI (Modified, Exclusive, Shared, Invalid) protocol or a variant thereof. The MESI protocol allows a cache line of data to be tagged with one of four states: 'M' (Modified), 'E' (Exclusive), 'S' (Shared), or 'I' (Invalid). The Modified state indicates that a memory block is valid only in the cache holding the Modified memory block and that the memory block is not consistent with system memory. The Exclusive state indicates that the associated memory block is consistent with system memory and that the associated cache is the only cache in the data processing system that holds the associated memory block. The Shared state indicates that the associated memory block is resident in the associated cache and possibly one or more other caches and that all of the copies of the memory block are consistent with system memory. Finally, the Invalid state indicates that the data and address tag associated with a coherency granule are both invalid."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In at least one embodiment, a coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.

"In at least one embodiment, a coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure.

"In at least one embodiment, a coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

"FIG. 1 is a high level block diagram of an exemplary data processing system in which a coherent device participates with a primary coherent system across a communication link through a proxy;

"FIG. 2 is a more detailed block diagram of an exemplary embodiment of the data processing system of FIG. 1;

"FIG. 3 is a more detailed block diagram of an exemplary embodiment of a processing unit in the data processing system of FIG. 2;

"FIG. 4 is a time-space diagram of an exemplary operation on the system fabric of the data processing system of FIG. 2;

"FIG. 5 is a more detailed block diagram of an exemplary embodiment of the coherent attached processor proxy (CAPP) in the processing unit of FIG. 3;

"FIG. 6 is a high level logical flowchart of an exemplary process by which a CAPP coherently handles a memory access request received from an attached processor (AP) in accordance with one embodiment;

"FIG. 7 is a high level logical flowchart of an exemplary process by which a CAPP coherently handles a snooped memory access request in accordance with one embodiment;

"FIG. 8 is a first time-space diagram of an exemplary processing scenario in which an AP requests to coherently update a memory block within the primary coherent system to which it is attached;

"FIG. 9 is a second time-space diagram of an exemplary processing scenario in which an AP requests to coherently update a memory block within the primary coherent system to which it is attached;

"FIG. 10 is a third time-space diagram of an exemplary processing scenario in which an AP requests to coherently update a memory block within the primary coherent system to which it is attached;

"FIG. 11 is a more detailed view of recovery circuitry within the CAPP of FIG. 5 in accordance with one embodiment;

"FIG. 12 is a high level logical flowchart of an exemplary process by which the recovery control sequencer of FIG. 11 directs recovery processing in a CAPP in accordance with one embodiment;

"FIG. 13 is a high level logical flowchart of an exemplary tag flush process by which a CAPP implements data recovery in accordance with one embodiment;

"FIG. 14 is a high level logical flowchart of an exemplary directory flush process by which a CAPP implements coherence state recovery in accordance with one embodiment;

"FIGS. 15-16 are high level logical flowcharts of exemplary processes by which flushing of selected CAPP directory entries is accelerated by reference to a demand queue in accordance with one embodiment; and

"FIG. 17 is a data flow diagram of an exemplary design process."

For additional information on this patent application, see: Blaner, Bartholomew; Cummings, David W.; Daly, JR., George W.; Siegel, Michael S.; Stuecheli, Jeff A. Accelerated Recovery for Snooped Addresses in a Coherent Attached Processor Proxy. Filed September 25, 2013 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=413&p=9&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Patents, Information Technology, Information and Data Processing, Information and Data Architecture, Information and Data Loss and Recovery.

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Source: Information Technology Newsweekly


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