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Patent Issued for Selective Re-Programming of Analog Memory Cells

August 5, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent by the inventors Sommer, Naftali (Rishon Le-Zion, IL); Perlmutter, Uri (Ra'anana, IL); Winter, Shai (Herzliya, IL), filed on July 2, 2012, was published online on July 22, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8787080 is assigned to Apple Inc. (Cupertino, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. This analog value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into intervals, each interval corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.

"Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible programming levels. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible programming levels.

"Flash memory devices are described, for example, by Bez et al., in 'Introduction to Flash Memory,' Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in 'Multilevel Flash Cells and their Trade-Offs,' Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.

"Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in 'Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?' Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in 'A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate', Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (RAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory--PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in 'Future Memory Technology including Emerging New Memories,' Proceedings of the 24.sup.th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An embodiment of the present invention provides a method for data storage, including:

"in a memory that includes multiple analog memory cells, defining an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states;

"initially storing data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states;

"after initially storing the data, programming a second group of the analog memory cells, which potentially cause interference to the first group; and

"after programming the second group, selectively re-programming the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset.

"In some embodiments, initially storing the data includes writing respective storage values into the memory cells in the first group and verifying the written storage values using first verification thresholds, and selectively re-programming the first group includes re-writing the storage values that are associated with the partial subset, and verifying the re-written storage values using second verification thresholds, higher than the corresponding first verification thresholds. In an embodiment, programming the memory cells includes writing respective storage values into the memory cells, and defining the partial subset includes including in the partial subset at least a non-erased programming state corresponding to a lowest range of the analog values among the non-erased memory states. In a disclosed embodiment, programming the memory cells includes writing respective storage values into the memory cells, and defining the partial subset includes including in the partial subset at least a non-erased programming state corresponding to a highest range of the analog values among the non-erased memory states.

"In some embodiments, the method includes programming the second group with dummy data responsively to detecting that programming of the second group is postponed, so as to cause re-programming of the first group. In an embodiment, detecting that the programming of the second group is postponed includes detecting that a time that elapsed since the programming of the second group exceeds a predefined maximum value. In another embodiment, detecting that the programming of the second group is postponed includes determining that shut-off of electrical power is imminent.

"In a disclosed embodiment, upon preparing to read the data from the first group, the method includes applying a corrective action to the first group responsively to detecting that that the first group was not re-programmed. Applying the corrective action may include programming the second group with dummy data, so as to cause re-programming of the first group. Additionally or alternatively, applying the corrective action may include sensing at least one analog value that was written into a respective analog memory cell in the first group and has become negative. Further additionally or alternatively, applying the corrective action may include applying one or more programming pulses to at least one of the memory cells in the first group.

"There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage, including:

"a memory, which includes multiple analog memory cells; and

"circuitry, which is configured to define an erased state, a set of non-erased programming states and a partial subset of the non-erased programming states, to initially store data in a first group of the analog memory cells by programming each of at least some of the memory cells in the first group from the erased state to a respective non-erased programming state selected from the set of non-erased programming states, to program a second group of the analog memory cells, which potentially cause interference to the first group, after initially storing the data, and, after programming the second group, to selectively re-program the first group with the data by repeating programming of only the memory cells in the first group whose respective programming states belong to the partial subset.

"The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

"FIGS. 2A-2C are graphs showing programming states and threshold voltage distributions in a group of analog memory cells, in accordance with embodiments of the present invention;

"FIG. 3 is a flow chart that schematically illustrates a method for selective re-programming of analog memory cells, in accordance with an embodiment of the present invention;

"FIG. 4 is a diagram that schematically illustrates a partially-programmed memory block, in accordance with an embodiment of the present invention; and

"FIG. 5 is a flow chart that schematically illustrates a method for data readout from a partially-programmed memory block, in accordance with an embodiment of the present invention."

URL and more information on this patent, see: Sommer, Naftali; Perlmutter, Uri; Winter, Shai. Selective Re-Programming of Analog Memory Cells. U.S. Patent Number 8787080, filed July 2, 2012, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8787080.PN.&OS=PN/8787080RS=PN/8787080

Keywords for this news article include: Apple Inc., Information Technology, Information and Data Storage.

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Source: Information Technology Newsweekly


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