The patent's assignee for patent number 8786309 is
News editors obtained the following quote from the background information supplied by the inventors: "This invention relates to integrated circuits, and more particularly, to integrated circuits having power gated functional blocks.
"As the number of transistors included on an integrated circuit 'chip' continues to increase, power management in the integrated circuits continues to increase in importance. Power management can be critical to integrated circuits that are included in mobile devices such as personal digital assistants (PDAs), cell phones, smart phones, laptop computers, net top computers, etc. These mobile devices often rely on battery power, and reducing power consumption in the integrated circuits can increase the life of the battery. Additionally, reducing power consumption can reduce the heat generated by the integrated circuit, which can reduce cooling requirements in the device that includes the integrated circuit (regardless of whether it is relying on battery power).
"Clock gating is often used to reduce dynamic power consumption in an integrated circuit, inhibiting a clock signal from being provided to idle circuitry. While clock gating is effective at reducing the dynamic power consumption, the idle circuitry may nevertheless remain powered on. Leakage currents in the idle transistors lead to static power consumption. The faster transistors (those that react to input signal changes, e.g. on the gate terminals) also tend to have the higher leakage currents which often results in high total leakage currents in the integrated circuit, especially in high performance devices.
"To counteract the effects of leakage current, some integrated circuits have implemented power gating. With power gating, the power to ground path of the idle circuitry is interrupted, reducing the leakage current to near zero. There can still be a small amount of leakage current through the switches used to interrupt the power, but it is substantially less than the leakage of the idle circuitry as a whole.
"Power gating presents challenges to the integrated circuit design. As blocks are powered up and powered down, the change in current flow to the blocks can create noise on the power supply connections. The noise can affect the operation of the integrated circuit, including causing erroneous operation. Additionally, the rate of change in the current flow varies with variations in the semiconductor fabrication process, the magnitude of the supply voltage provided to the integrated circuit, and the operating temperature of the integrated circuit. When these factors slow the rate of change of the current, the delay incurred in enabling a power gated block may increase correspondingly."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "A multi-path power switch scheme for functional circuit block wakeup is disclosed. The scheme as disclosed herein may be applied within a single functional circuit block as well as to multiple functional blocks.
"In one embodiment, a power gated functional block of an integrated circuit includes first and second groups of power switches coupled between a global voltage node and a local voltage node (e.g., a global supply voltage node and a local supply voltage node). During a power on procedure, the first group of switches may be activated sequentially. After a predetermined time has elapsed from initiating activation of the first group of switches, sequential activation of the second group of switches is initiated. A timer may indicate when the predetermined time has elapsed.
"In an embodiment of an integrated circuit having multiple power gated circuit blocks, a first power gated functional block may be powered on responsive to assertion of a first enable signal. For a predetermined amount of time subsequent to initiating the power on procedure for the first functional block, a power control unit may, for a predetermined time, inhibit the initiation of a power on procedure for any of the other power gated functional blocks that are not currently powered (or powering) up. After the predetermined time period has elapsed, the power control unit may initiate a power up procedure for a next functional block to be powered up. The interval between the first power switch enable and the second power switch enable may be predetermined such that the additional current from the second group of power switches does not cause the total current to exceed the max current and max di/dt during only the first group of power switches are enabled at the fast PVT condition.
"Within a given functional block, each of the power switches may be implemented as transistors coupled between the global voltage node and a local voltage node exclusive to that functional block. Each of the first group of transistors may be coupled to corresponding ones of a first group of serially-coupled delay elements. Each of the second group of transistors may be coupled to corresponding ones of a second group of serially-coupled delay elements. The power on procedure for the functional block may be initiated by providing the enable signal to the first group of delay elements. As the enable signal propagates through the chain formed by the first group of serially-coupled delay elements, the transistors of the first group are sequentially activated. When the predetermined time has elapsed (as indicated by the timer), an enable signal may be provided to the second group of serially-coupled delay elements, thereby initiating sequential activation of the second group of transistors.
"Powering up transistors sequentially and in groups within a functional block may control current received into the functional block during the power on procedure. This in turn may control the amount of power supply noise (which is a product of inductance and the change in current) produced during the powering on of a functional block. Similarly, powering on functional blocks sequentially and limiting the amount of time of overlap when concurrently powering on two functional block may also control the amount of power supply noise by controlling transient current within the integrated circuit."
For additional information on this patent, see: Takayanagi, Toshinari;
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