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Patent Issued for Fast Analog Memory Cell Readout Using Modified Bit-Line Charging Configurations

August 5, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- A patent by the inventors Gurgi, Eyal (Petah-TikvaIL, IL); Shur, Yael (Tel Aviv, IL); Kasorla, Yoav (Even Yehuda, IL), filed on December 10, 2012, was published online on July 22, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8787057 is assigned to Apple Inc. (Cupertino, CA).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Various techniques for reading analog memory cells are known in the art. For example, U.S. Pat. No. 8,059,457, whose disclosure is incorporated herein by reference, describes a method for data storage. The method includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An embodiment of the present invention that is described herein provides a method for data storage. The method includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.

"In some embodiments, the first readout scheme causes the bit lines to be charged at a first rate, and the second readout scheme causes the bit lines to be charged at a second rate, faster than the first rate. In an embodiment, the first readout scheme specifies first voltages to be applied to the respective bit lines while charging the bit lines, and the second readout scheme specifies second voltages to be applied to the respective bit lines while charging the bit lines, such that at least one of the second voltages is higher than a corresponding one of the first voltages. In another embodiment, reading the storage values includes, after the bit lines are charged using the selected readout scheme, allowing the bit lines to discharge and sensing the discharged bit lines.

"In some embodiments, reading the storage values includes sensing respective electrical currents flowing through the bit lines. In an embodiment, the first readout scheme specifies that the electrical currents are to be sensed after a first time delay relative to a beginning of charging the bit lines, and the second readout scheme specifies that the electrical currents are to be sensed after a second time delay, smaller than the first time delay. In another embodiment, the second readout scheme specifies the second time delay such that the bit lines are not fully charged when the electrical currents are sensed.

"In a disclosed embodiment, the memory cells in the group belong to a word line selected from among multiple word lines, the first readout scheme applies first pass voltages to the word lines other than the selected word line while reading the group of memory cells, and the second readout scheme applies second pass voltages to the word lines other than the selected word line, such that at least one of the second pass voltages is higher than a corresponding one of the first pass voltages.

"In another embodiment, the memory cells in the group belong to a word line, the first readout scheme applies a first voltage to the word line while reading the group of memory cells, and the second readout scheme applies a second voltage to the word line, higher than the first voltage. In yet another embodiment, the analog memory cells are implemented in a memory device, and reading the storage values includes sending to the memory device a command that indicates the selected readout scheme.

"There is additionally provided, in accordance with an embodiment of the present invention, apparatus for data storage, including circuitry and a plurality of analog memory cells. The circuitry is configured to evaluate a condition with respect to a read operation that is to be performed over a group of the memory cells that are connected to respective bit lines, to select, responsively to the evaluated condition, between at least first and second readout schemes for reading storage values from the analog memory cells, such that the first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and such that the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time that is shorter than the first sense time, and to read the storage values from the group of the memory cells using the selected readout scheme.

"There is also provided, in accordance with an embodiment of the present invention, apparatus for data storage including an interface and circuitry. The interface is configured for communicating with a memory including a plurality of analog memory cells. The circuitry is configured to evaluate a condition with respect to a read operation that is to be performed over a group of the memory cells that are connected to respective bit lines, to select, responsively to the evaluated condition, between at least first and second readout schemes for reading storage values from the analog memory cells, such that the first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and such that the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time that is shorter than the first sense time, and to read the storage values from the group of the memory cells using the selected readout scheme.

"The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention;

"FIGS. 2-4 are graphs showing bit-line charging configurations for normal and fast readout, in accordance with embodiments of the present invention; and

"FIG. 5 is a flow chart that schematically illustrates a method for memory cell readout, in accordance with an embodiment of the present invention."

URL and more information on this patent, see: Gurgi, Eyal; Shur, Yael; Kasorla, Yoav. Fast Analog Memory Cell Readout Using Modified Bit-Line Charging Configurations. U.S. Patent Number 8787057, filed December 10, 2012, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8787057.PN.&OS=PN/8787057RS=PN/8787057

Keywords for this news article include: Apple Inc., Information Technology, Information and Data Storage.

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Source: Information Technology Newsweekly


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