News Column

"Metal-Programmable Integrated Circuits" in Patent Application Approval Process

August 7, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- A patent application by the inventors Gan, Chong Gim (Gelugor, MY); Phoon, Hee Kong (Bagan Serai, MY); Voon, Sean Woei (Bukit Mertajam, MY), filed on January 15, 2013, was made available online on July 24, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Altera Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Integrated circuits are often designed to perform desired functions. During manufacturing, a mask is typically used to produce circuitry on the integrated circuit (e.g., using photolithography and other manufacturing techniques). Circuitry on an application-specific integrated circuit (ASIC) is formed using specialized masks that are generated for producing specific circuit structures. The specialized ASIC masks may be used to generate multiple identical integrated circuits, which tends to reduce the overall cost. For example, hundreds, thousands, millions, or more integrated circuits may be manufactured using the specialized masks. However, a specialized ASIC mask is expensive and is only capable of producing identical integrated circuits.

"Metal-programmable gate arrays can help to reduce manufacturing costs. Different cells of the metal-programmable gate arrays are interconnected to form circuits that perform logic functions. Each cell of the metal-programmable gate array has circuit attributes such as drive strength that are predetermined and fixed. Such cell structures can lead to inefficient use of integrated circuit resources due to mismatch between desired circuit attributes and fixed cell attributes."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may be formed with identical transistor structures that form a base layer of the metal-programmable integrated circuit. The transistor structures of each cell may be formed from multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure. The multi-gate transistor structures may form one or more fin-shaped field effect transistors (FinFETs). The gate structure may at least partially enclose multiple channel structures that serve as fins of a FinFET transistor. Pairs of source-drain structures may be coupled to the channel structures. If desired, multiple gate structures may share some of the source-drain structures.

"The transistor structures of each cell may be formed in a substrate. One or more metal interconnect layers may cover the substrate. Paths formed in the metal interconnect layers may configure the cells to perform desired logic functions. The paths associated with a given cell may be selectively coupled to transistor structures of the cell such as the gate and source-drain structures to configure the cell for a desired logic function and/or for desired output drive strength.

"The transistor structures of the array of metal-programmable cells may be formed using a base layer mask. The array of metal-programmable cells may be subsequently configured to perform logic functions of a custom logic design. The array of metal-programmable cells may be configured by using a metal layer mask to form appropriate paths in the metal interconnect layers.

"Further features of the present invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a diagram of an illustrative metal-programmable integrated circuit in accordance with an embodiment of the present invention.

"FIG. 2 is a cross-sectional view of an illustrative metal-programmable integrated circuit in accordance with an embodiment of the present invention.

"FIG. 3 is a perspective view of illustrative multi-gate transistor structures of metal-programmable integrated circuit in accordance with an embodiment of the present invention.

"FIG. 4 is a layout diagram of illustrative multi-gate transistor structures having a single gate structure in accordance with an embodiment of the present invention.

"FIG. 5 is a layout diagram of illustrative multi-gate transistor structures having multiple gate structures with shared source-drain structures in accordance with an embodiment of the present invention.

"FIG. 6 is a layout diagram of illustrative multi-gate transistor structures that have been metal-programmed in accordance with an embodiment of the present invention.

"FIG. 7 is an illustrative circuit diagram of the metal-programmed transistor structures of FIG. 6 in accordance with an embodiment of the present invention.

"FIG. 8 is a layout diagram of an illustrative metal-programmable cell configured as an inverter with unit output drive strength in accordance with an embodiment of the present invention.

"FIG. 9 is an illustrative circuit diagram of the metal-programmable cell configured as an inverter with unit output drive strength of FIG. 8 in accordance with an embodiment of the present invention.

"FIG. 10 is a layout diagram of an illustrative metal-programmable cell configured as an inverter with increased output drive strength in accordance with an embodiment of the present invention.

"FIG. 11 is an illustrative circuit diagram of the metal-programmable cell configured as an inverter with increased output drive strength of FIG. 10 in accordance with an embodiment of the present invention.

"FIG. 12 is a layout diagram of an illustrative metal-programmable cell configured as an inverter with reduced output drive strength in accordance with an embodiment of the present invention.

"FIG. 13 is an illustrative circuit diagram of the metal-programmable cell configured as an inverter with reduced output drive strength of FIG. 8 in accordance with an embodiment of the present invention.

"FIG. 14 is a layout diagram of an illustrative metal-programmable cell configured as a logic NOR gate in accordance with an embodiment of the present invention.

"FIG. 15 is an illustrative circuit diagram of the metal-programmable cell configured as a logic NOR gate of FIG. 14 in accordance with an embodiment of the present invention.

"FIG. 16 is a layout diagram of an illustrative metal-programmable cell configured as a logic NAND gate in accordance with an embodiment of the present invention.

"FIG. 17 is an illustrative circuit diagram of the metal-programmable cell configured as a logic NAND gate of FIG. 16 in accordance with an embodiment of the present invention.

"FIG. 18 is a layout diagram of an illustrative metal-programmable cell configured as a signal bus in accordance with an embodiment of the present invention.

"FIG. 19 is an illustrative circuit diagram of the metal-programmable cell configured as a signal bus of FIG. 18 in accordance with an embodiment of the present invention.

"FIG. 20 is a diagram of illustrative steps that may be performed to manufacture and configure a metal-programmable integrated circuit in accordance with an embodiment of the present invention.

"FIG. 21 is a flow chart of illustrative steps that may be performed to manufacture and configure a metal-programmable integrated circuit in accordance with an embodiment of the present invention."

URL and more information on this patent application, see: Gan, Chong Gim; Phoon, Hee Kong; Voon, Sean Woei. Metal-Programmable Integrated Circuits. Filed January 15, 2013 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4415&p=89&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Altera Corporation.

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Source: Politics & Government Week


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