News Column

Researchers Submit Patent Application, "Three-Dimensional Semiconductor Devices and Methods of Fabricating the Same", for Approval

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors PARK, Jintaek (Hwaseong-si, KR); KANAMORI, Kohji (Seoul, KR); PARK, Youngwoo (Seoul, KR); LEE, Jaeduk (Seongnam-si, KR), filed on January 10, 2014, was made available online on July 24, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments of inventive concepts relate to a semiconductor device, and for example, to three-dimensional semiconductor devices and/or methods of fabricating the same.

"In semiconductor devices, increased integration may be an important factor in realizing a high performance and/or a low cost device. Currently, in a two-dimensional memory semiconductor device or in a planar memory semiconductor device, integration may be affected by forming a fine pattern, since integration may determine an area that a unit memory cell occupies. However, equipment used to form a fine pattern may be expensive so economic factors may limit increasing integration of a two-dimensional memory semiconductor device. Thus, three-dimensional memory devices (e.g., three-dimensionally arranged memory cells) are being developed."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Example embodiments of inventive concepts relate to a three-dimensional semiconductor memory device with an increased page depth.

"Example embodiments of inventive concepts relate to a three-dimensional semiconductor memory device capable of reducing a parasitic resistance of an active pattern thereof.

"Example embodiments of inventive concepts relate to a fabricating method capable of reducing a capacitive coupling between word lines of a three-dimensional semiconductor memory device.

"Example embodiments of inventive concepts relate to a fabricating method capable of improving a data retention property of a three-dimensional semiconductor memory device.

"According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array, and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

"In example embodiments, the string selection line decoder may be between the memory cell array and the page buffer.

"In example embodiments, the memory cell array may be between the string selection line decoder and the page buffer.

"In example embodiments, the device may further include: a plurality of bit lines crossing the memory cell array and connected to the page buffer; a plurality of string selection lines crossing the memory cell array and connected to the string selection line decoder; and a plurality of word lines crossing the memory cell array and connected to a corresponding one of the at least one word line decoder. The plurality of bit lines and the plurality of string selection lines may cross the plurality of word lines.

"In example embodiments, the memory cell array may include a plurality of blocks arranged along a longitudinal direction of the plurality of bit lines, and each of the blocks may include a plurality of sectors arranged along a longitudinal direction of the plurality of word lines.

"In example embodiments, the memory cell array may include block selection lines in the plurality of blocks, respectively, and the block selection lines may be configured to control electric connections between the plurality of bit lines and block units of the memory cells.

"In example embodiments, the memory cell array may include active patterns. The active patterns may have a multi-layered and a multi-column structure. In each of the plurality of blocks, the active patterns of two different sectors of the plurality of sectors may be separated from each other in the longitudinal direction of the plurality of word lines.

"In example embodiments, the device may further include: a plurality of bit line contact plugs, each being configured to connect one of the plurality of bit lines electrically to a corresponding one of the layers in a corresponding one of the active patterns. An adjacent pair of the plurality of blocks may share some of the plurality of bit line contact plugs.

"In example embodiments, a number of the plurality of bit line contact plugs in each of the sectors may be half a number of the layers of the active patterns in each of the sectors.

"In example embodiments, the device may further include a plurality of bit line contact plugs, each being configured to connect one of the plurality of bit lines electrically to a corresponding one of the plurality of layers of the active patterns. An adjacent pair of the plurality of blocks may be connected to the plurality of bit lines through different bit line contact plugs among the plurality of bit line contact plugs.

"In example embodiments, a number of the plurality of bit line contact plugs may be equal to a number of the layers in the plurality of active patterns in each of the plurality of sectors.

"In example embodiments, the memory cell array may include: active patterns including a multi-layered and a multi-column structure; word lines crossing the active patterns and having a multi-column structure; and a charge storing layer between the active patterns and the word lines.

"In example embodiments, the memory cell array may include active patterns, the active patterns may have a multi-layer and a multi-column structure, each of the active patterns may be a semiconductor pattern, whose longitudinal axis may be parallel to a substrate, and each of the plurality of word lines may include vertical gates between the active patterns and a horizontal line connecting the vertical gates.

"In example embodiments, each of the plurality of bit lines may be electrically connected to a corresponding one of the active patterns, and each of the string selection lines may be configured to control electric connections between the plurality of bit lines and a corresponding column in one of the active patterns.

"In example embodiments, the device may further include low resistance layers connected to the layers, respectively, of the plurality of active patterns, and bit line contact plugs connecting each of the bit lines electrically to a corresponding one of the low resistance layers. A resistivity of the low resistance layers may be lower than a resistivity of the plurality of active patterns.

"In example embodiments, an adjacent pair of the plurality of blocks may share one of the low resistance layers, and at least one replacement opening may vertical penetrate the low resistance layers.

"In example embodiments, the device may further include bit line contact plugs connecting each of the bit lines electrically to a corresponding one of the layers of the active patterns. The bit line contact plugs may be substantially a same distance from one of the plurality of word lines.

"According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: active patterns having a multi-layered and a multi-column structure; word lines having a multi-column structure, the word lines crossing the active patterns; and string selection gates configured to control the columns of the active patterns, respectively. The string selection gates include first gates located at a first distance and second gates located at a second distance, the second distance being smaller than the first distance, when measured from a most adjacent one of the word lines that may be located closest to the string selection gates, and the most adjacent word line may include a plurality of first extended portions extending toward the first gates.

"In example embodiments, the device may further include a block selection line spaced apart from the most adjacent word line by the string selection gates, and the block selection line may include second extended portions protruding toward the second gates.

"In example embodiments, the string selection gates may be on the columns of the active patterns.

"In example embodiments, the string selection gates may be between the columns of the active patterns.

"According to example embodiments of inventive concepts, a method of fabricating a three-dimensional semiconductor device may include forming active patterns having a multi-layered and a multi-column structure; forming a memory layer having a multi-layered structure to cover the active patterns; forming word lines having a multi-column structure, the word line crossing the active patterns; and etching at least a portion of the memory layer exposed between the word lines.

"In example embodiments, the memory layer may include a tunnel insulating layer, a charge storing layer, and a blocking insulating layer that may be sequentially stacked, and the etching of at least a portion of the memory layer may remove at least one of the tunnel insulating layer, the charge storing layer, and the blocking insulating layer from between the word lines.

"In example embodiments, the method may further include: forming an insulating gapfill layer between the word lines after the etching of at least the portion of the memory layer. The insulating gapfill layer may define an air-gap between the word lines and the active patterns.

"According to example embodiments of inventive concepts, a method of fabricating a three-dimensional semiconductor device may include forming active patterns having a multi-layered and a multi-column structure, forming word lines having a multi-column structure, the word lines crossing the active patterns, and forming an insulating gapfill layer between the word lines. The insulating gapfill layer may define an air-gap between the word lines and the active patterns.

"In example embodiments, each of the word lines may include: vertical gates between the columns of the active patterns, the vertical gates facing sidewalls of the active patterns; and a horizontal line connecting the vertical gates to each other in a direction crossing the active patterns. The air-gap may be locally formed between the vertical gates.

"According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that are stacked on top of each other, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to one of the bottom and top sides of the memory cell array; and a string selection line decoder adjacent to one of, the one of the bottom and top sides of the memory cell array, or a different one of the bottom and top sides of the memory cell array.

"In example embodiments, the device may include: a plurality of string selection gates; a plurality of bit lines crossing the memory cell array and connected to the page buffer; a plurality of string selection lines crossing the memory cell array in a direction parallel to the plurality of bit lines and connected to the string selection line decoder; a plurality of word line crossing the memory cell array and connected to the at least one word line decoder. Blocks units of the memory cell array may include a plurality of active pattern layers stacked vertically on top of each other. Each one of the plurality of active pattern layers may include columns that extend in the direction parallel to the plurality of bit lines and define spaces between the columns. Each one of the word lines may include a plurality of vertical portions that extend vertically through the spaces between the columns in the plurality of active pattern layers. Each one of the string selection gates may be configured to control a connection between one of the plurality of bit lines and one of the columns in one of the plurality of active pattern layers.

"In example embodiments, the device may include a plurality of bit line contact plugs, and each one of the plurality of bit line contact plugs may be configured to connect the plurality of bit lines to a corresponding one of the active pattern layers.

"In example embodiments, an adjacent pair of blocks units in the memory cell array may share some of the plurality of bit line contact plugs in common.

"In example embodiments, one of the plurality of word lines crossing each block unit of the memory cell array may be a dummy word line that includes extended portions that extend perpendicular from the dummy word line and alternate with non-extended portions of the dummy word line. The string selection gates may include a first group of string selection gates spaced apart from the extended portions of the dummy word line and a second group of string selection gates spaced apart from the non-extended portions of the dummy word line in each block unit of the memory cell array, and the first group of string selection gates and the second group of string selection gates may be arranged in a zig zag pattern in the plan view.

BRIEF DESCRIPTION OF THE DRAWINGS

"Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.

"FIGS. 1 through 4 are schematic chip layout diagrams depicting three-dimensional semiconductor memory devices according to example embodiments of inventive concepts.

"FIG. 5 is a schematic diagram illustrating a memory cell array of a three-dimensional semiconductor memory device according to example embodiments of inventive concepts.

"FIGS. 6 through 12 are plan views illustrating memory cell arrays of three-dimensional semiconductor memory devices, according to example embodiments of inventive concepts.

"FIGS. 13 through 15 are perspective views illustrating memory cell arrays of three-dimensional semiconductor memory devices, according to example embodiments of inventive concepts.

"FIG. 16 is a perspective view illustrating active patterns of a three-dimensional semiconductor memory device, according to example embodiments of inventive concepts.

"FIGS. 17 and 18 are plan views illustrating a memory cell array of a three-dimensional semiconductor memory device, according to example embodiments of inventive concepts.

"FIG. 19 is a flow chart illustrating a method of fabricating a three-dimensional semiconductor memory device according to example embodiments of inventive concepts.

"FIG. 20 is a perspective view illustrating a three-dimensional semiconductor memory device according to example embodiments of inventive concepts, which is fabricated using the fabricating method of FIG. 19.

"FIG. 21 is an enlarged view of a portion of the three-dimensional semiconductor memory device in FIG. 20.

"FIG. 22 is a flow chart illustrating a method of fabricating a three-dimensional semiconductor memory device, according to example embodiments of inventive concepts.

"FIG. 23 is a sectional view illustrating a three-dimensional semiconductor memory device according to example embodiments of inventive concepts, which is fabricated using the fabrication method of FIG. 22.

"FIGS. 24 and 25 are block diagrams schematically illustrating electronic devices including a semiconductor device according to example embodiments of inventive concepts.

"It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature."

For additional information on this patent application, see: PARK, Jintaek; KANAMORI, Kohji; PARK, Youngwoo; LEE, Jaeduk. Three-Dimensional Semiconductor Devices and Methods of Fabricating the Same. Filed January 10, 2014 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3326&p=67&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Patents, Electronics, Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters