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Researchers Submit Patent Application, "Ten-Transistor Dual-Port Sram with Shared Bit-Line Architecture", for Approval

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors HWANG, Wei (Hsinchu, TW); WANG, Dao-Ping (Hsinchu, TW), filed on April 24, 2013, was made available online on July 24, 2014.

The patent's assignee is National Chiao Tung University.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to the technical of dual-port static random access memory (SRAM) and, more particularly, to a ten-transistor (10T) dual-port SRAM with shared bit-line architecture.

"In recent years, the IC design demands more transmission bandwidths, such that the memory requirement is evolved from a single-port SRAM into a dual-port SRAM. Because of having advanced feature of parallel operation for high speed communication and video applications which the single-port SRAM does not have, the dual-port SRAM can perform a parallel read or write operation on different ports, but it introduces read/write disturb issues in the same row access.

"FIGS. 1(A)-1(D) schematically illustrate an access of a conventional dual-port SRAM. FIG. 1(A) shows an access to an A-port and a B-port at different rows and different columns. FIG. 1(B) shows an access to the A-port and the B-port at different rows and the same column. As shown in FIGS. 1(A) and 1(B), both of the access modes activate only single port on one row. Namely, when an activated memory cell of a word line WL is operated as a single-port access, no access conflict occurs to the access modes of FIGS. 1(A) and 1(B).

"FIG. 1(C) shows an access to the A-port and the B-port at the same row and different columns. FIG. 1(D) shows an access to the A-port and the B-port at the same row and the same column. In this case, there is an access conflict on the access modes of FIGS. 1(C) and 1(D).

"FIG. 1(C) shows that, when the memory cell 110 on the left of row 1 executes a read/write operation at the A-port, the A-port of the memory cell 120 becomes a dummy read, with the bit lines BL pre-charged to high. When the B-port attempts to write a low voltage (0) in the memory cell 120 through the bit line, the internal storage node of the memory cell 120 is difficult to change its storage state, which is referred to as a write data disturb.

"FIG. 2 shows a schematic diagram of a conventional write data disturb. For an access to the memory cells 110, 120, all the bit lines are pre-charged to a high voltage (1). When the A-port attempts to execute a read/write operation on the left, i.e., the memory cell 110, the word line WL, i.e., AWL1, is first activated to the high voltage (1). In this case, when the B-port attempts to write a low voltage (0) in the memory cell 120 through the bit line BBL2, the word line WL, i.e., BWL1, is activated to a high voltage (H), and the bit line BBL2 is low (0). Since the word lines AWL1 and BWL1 are high (1), the transistors N1 and N2 are all turned on, so as to bring the bit line ABL2 to high (1) and the bit line BBL2 to low (0). Thus, the bit line ABL2 is pulled up, so that the internal storage node X of the memory cell 120 is difficult to change its storage state.

"FIG. 3 shows a schematic diagram of a conventional read data disturb. For an access to the memory cells 110, 120, all the bit lines are pre-charged to a high voltage (1). When the A-port attempts to execute a read/write operation on the left, i.e., the memory cell 110, the word line WL, i.e., AWL1, is first activated to the high voltage (1), and the transistor N1 is turned on. Since the word line ABL2 is pre-charged to high (1), the internal storage node X is slightly pulled up to a voltage, denoted as 0+, by the bit line ABL2 as it stores a data with the low voltage (0), so that a read data disturb occurs. Namely, when the voltage 0+ of the internal storage node X of the memory cell 120 is read through the bit line BBL2 and amplified by a sensing amplifier, it can easily cause an erroneous read data.

"To overcome the write data disturb and the read data disturb, in Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, and Hirofumi Shinohara, 'Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access,' IEEE Journal of Solid-State Circuits, Vol. 44, No, 3, March 2009, pp. 977-986, it uses a row-address comparator to detect whether the same row is accessed and, if yes, the B-port row decoder is turned off to avoid the conflict of concurrently accessing the A-port and the B-port. However, such a way reduces the entire access efficiency and has to add the column-address comparator and peripherals, resulting in increased cost.

"Accordingly it is desirable to provide an improved dual-port SRAM to mitigate and/or obviate the aforementioned problems."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The object of the present invention is to provide a ten-transistor (10T) dual-port SRAM with shared bit-line architecture, which can share adjacent bit lines, cancel read/write disturb, and expand the static noise margin. Furthermore, the total number of bit lines can be reduced to half so as to reduce the read/write power consumption on charging a bit line. As compared with the conventional 8T dual-port SRAM, the present invention can reduce the bit-line leakage.

"According to a feature of the present invention, there is provided a ten-transistor (10T) dual-port SRAM with shared bit-line architecture, which includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set. The first switch set is connected to a first A-port bit line, a first B-port bit line, and the first storage unit. The second switch set is coupled to a complement first A-port bit line and a complement first B-port bit line, and connected to the first storage unit. The second memory cell has a second storage unit, a third switch set, and a fourth switch set. The third switch set is connected to the complement first A-port bit line, the complement first B-port bit line, and the second storage unit. The fourth switch set is coupled to a second A-port bit line and a second B-port bit line, and connected to the second storage unit. Thus, the second memory cell can make use of the third switch set to share the complement first A-port bit line and the complement first B-port bit line with the first memory cell.

"According to another feature of the present invention, there is provided a ten-transistor (10T) dual-port SRAM with shared bit-line architecture, which includes a storage unit, a first switch set, and a second switch set. The storage unit is comprised of a latch and has a first storage node and a second storage node. The first switch set includes first to fourth switches. The first switch has one end connected to a first A-port bit line, a control terminal connected to an A-port word line, and the other end connected to one end of the second switch. The second switch has the other end connected to the first storage node and a control terminal connected to a first-column A-port control line. The third switch has one end connected to a first B-port bit line, a control terminal connected to a B-port word line, and the other end connected to one end of the fourth switch. The fourth switch has the other end connected to the first storage node and a control terminal connected to a first-column B-port control line. The second switch set includes fifth to sixth switches. The fifth switch has one end connected to the second storage node and a control terminal connected to the first-column A-port control line. The sixth switch has one end connected to the second storage node and a control terminal connected to the first-column B-port control line.

"Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIGS. 1(A)-1(D) schematically illustrate an access of a conventional dual-port SRAM;

"FIG. 2 shows a schematic diagram of a conventional write data disturb;

"FIG. 3 shows a schematic diagram of a conventional read data disturb;

"FIG. 4 is a schematic diagram of a ten-transistor (10T) dual-port SRAM with shared bit-line architecture according to the invention;

"FIG. 5 is a schematic diagram of a dual-port SRAM cell according to the invention;

"FIG. 6 is a schematic diagram of concurrently accessing A-port and B-port of a ten-transistor (10T) dual-port SRAM with shared bit-line architecture according to the invention;

"FIGS. 7(A) and 7(B) schematically illustrate a comparison of current consumption between the present invention and the prior art;

"FIG. 8 is a schematic diagram of a current leakage path according to the invention; and

"FIG. 9 schematically illustrates a comparison of current leakage between the present invention and the prior art."

For additional information on this patent application, see: HWANG, Wei; WANG, Dao-Ping. Ten-Transistor Dual-Port Sram with Shared Bit-Line Architecture. Filed April 24, 2013 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3316&p=67&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Electronics, High Voltage, National Chiao Tung University.

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Source: Electronics Newsweekly


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