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Researchers Submit Patent Application, "Solid-State Image Sensor", for Approval

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Araoka, Yukio (Hiratsuka-shi, JP); Shingai, Satoru (Tama-shi, JP), filed on March 18, 2014, was made available online on July 24, 2014.

The patent's assignee is Canon Kabushiki Kaisha.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a solid-state image sensor.

"The basic arrangement of a solid-state image sensor 1 will be described with reference to FIG. 1. The solid-state image sensor 1 comprises a pixel array 10 including a plurality of pixel units 11, and a signal processing circuit 20 for amplifying a signal output from the pixel array 10 to a column signal line 2. In each pixel unit 11, a transfer transistor TX transfers, for example, charges generated by the energy of light received by a photodiode PD to the gate of a source follower transistor SF. Then, the source follower transistor SF outputs a signal corresponding to the transferred charges to the column signal line 2 via a selection transistor SEL. Each pixel unit 11 can include a reset transistor RES for resetting the potential of the gate of the source follower transistor SF to a predetermined voltage.

"The signal processing circuit 20 is used to amplify the signal output from each pixel unit 11 to the column signal line 2. The signal processing circuit 20 includes an operation amplifier 21 having an input terminal 22 and an output terminal 23, an input capacitance C0 inserted between the input terminal 22 and the column signal line 2, and a feedback capacitor Cf connecting the input terminal 22 to the output terminal 23. The amplification factor of the signal processing circuit 20 is determined based on a capacitance ratio C0/Cf. To change the amplification factor, for example, to switch the sensitivity setting of a digital still camera, it is only necessary to change the ratio C0/Cf. To change the amplification factor from, for example, 32 to 128, it is only necessary to increase the value of C0 by a factor of four or decrease the value of Cf to a quarter.

"To improve the sensitivity of light detection, a high amplification factor is required for the signal processing circuit 20. This especially applies to a case in which a signal output to the column signal line 2 becomes very weak due to the reduction in the size of a photoelectric conversion element such as the photodiode PD or a case in which the sensitivity of a camera having the solid-state image sensor 1 is set to be higher. To increase the amplification factor of the signal processing circuit 20, it is generally necessary (1) to increase the value of C0, (2) to decrease the value of Cf, or (3) to increase the value of C0 and decrease the value of Cf. However, increasing the capacitance value may cause an increase in chip area, and decreasing the capacitance value may cause a production variation."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present invention provides a technique which is advantageous in increasing an amplification factor while suppressing an increase in chip area and a production variation.

"One of the aspects of the present invention provides a solid-state image sensor comprising a pixel array having a plurality of pixels, and a plurality of signal processing circuits each of the plurality of signal processing circuits amplifying a signal output from the pixel array to a plurality of column signal lines, wherein each of the plurality of signal processing circuits comprises an operation amplifier which has an input terminal and an output terminal, an input capacitance arranged between the input terminal and the column signal line, and a feedback circuit which connects the input terminal with the output terminal, wherein the feedback circuit is configured to form a feedback path in which a first capacitance element and a second capacitance element are arranged in series in a path connecting the input terminal to the output terminal, and a third capacitance element is arranged between a reference potential and a path connecting the first capacitance element to the second capacitance element.

"Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a circuit diagram for explaining a solid-state image sensor according to the prior art;

"FIG. 2 is a circuit diagram showing an example of a solid-state image sensor for explaining the present invention;

"FIG. 3 is a graph showing an amplification variation for explaining the effects of the present invention;

"FIG. 4 is a circuit diagram showing an example of a solid-state image sensor for explaining the present invention;

"FIG. 5 is a circuit diagram showing an example of a solid-state image sensor for explaining the present invention; and

"FIG. 6 is a circuit diagram showing an example of a signal processing circuit to which the present invention is applied."

For additional information on this patent application, see: Araoka, Yukio; Shingai, Satoru. Solid-State Image Sensor. Filed March 18, 2014 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4575&p=92&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Electronics, Signal Processing, Canon Kabushiki Kaisha.

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Source: Electronics Newsweekly


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