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Researchers Submit Patent Application, "Semiconductor Device Having Dual Parallel Channel Structure and Method of Fabricating the Same", for Approval

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors UM, Chang-yong (Seoul, KR); SHIN, Jai-kwang (Anyang-si, KR), filed on August 6, 2013, was made available online on July 24, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present disclosure relates to a semiconductor device having a dual parallel channel structure and a method of fabricating the same. More particularly, the present disclosure relates to a high power semiconductor device having a dual parallel channel structure capable of reducing an On-resistance and preventing a relatively large electric field from being applied to a gate oxide layer under a gate and a method of fabricating the same.

"In a power converting system for receiving a main power to be converted into a voltage required for a plurality of devices or to be distributed, the function of a power switching device is important. For example, the power switching device may be realized by a transistor based on a semiconductor material such as silicon, GaN, or SiC, like a metal oxide semiconductor field effect transistor (MOSFET). The power switching device is required to have a relatively high breakdown voltage. A large amount of research on the power switching device is being conducted in order to obtain characteristics of reduction in an On-resistance, high density integration, and rapid switching.

"For example, a field effect transistor (FET) of a trench gate structure, in which a trench is vertically formed and a gate oxide layer and a gate are formed in the trench, is advantageous in terms of high current and high density integration. However, in the FET of the trench gate structure, since the gate oxide layer under the gate is exposed to a drain formed under a substrate, when a high voltage is applied to the drain in an Off state, a large electric field is concentrated on the gate oxide layer under the gate. Therefore, insulation breakdown may be generated by the gate oxide layer before reaching the breakdown voltage.

"On the other hand, it is relatively difficult to put the MOSFET using SiC into commercial use due to the relatively low channel mobility. Therefore, for example, research on improving mobility through a nitridation process is being conducted. However, since a threshold voltage is lowered as the mobility is increased, there are limitations to improving the mobility."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present disclosure relates to a high power semiconductor device having a dual parallel channel structure capable of minimizing reduction in a threshold voltage, reducing an On-resistance, and reducing or preventing a relatively large electric field from being applied to a gate oxide layer thereunder.

"The present disclosure also relates to a method of fabricating the high power semiconductor device.

"According to an example embodiment, a semiconductor device may include a substrate having a drift region doped to a first conduction type, a trench formed by vertically etching an upper surface of the substrate, a gate arranged along side walls of the trench, a gate oxide layer arranged between the side walls of the trench and the gate and between a bottom surface of the trench and the gate, a first source region of the first conduction type formed on the upper surface of the substrate, a second source region of the first conduction type formed on the bottom surface of the trench, a first well region formed between the first source region and the drift region, and a second well region formed between the second source region and the drift region, wherein the first and second well regions are doped to a second conduction type which is electrically opposite to the first conduction type.

"The semiconductor device may further include a drain electrode arranged on a lower surface of the substrate, a source electrode formed on the substrate and in the trench so as to be electrically connected to the first and second source regions, and an interlayer insulating layer that covers the gate and the gate oxide layer so that the gate and the gate oxide layer do not contact the source electrode.

"The semiconductor device may further include a first ohmic contact layer arranged between the first well region and the source electrode so as to provide an ohmic contact between the source electrode and the first source region and a second ohmic contact layer arranged in a central portion of the second source region so as to be adjacent to the second source region in order to provide ohmic contact between the source electrode and the second source region.

"The first ohmic contact layer may be arranged on the first well region so as to be adjacent to the first source region. The second ohmic contact layer may be arranged on the second well region so as to be adjacent to the second source region.

"The first and second ohmic contact layers may be second conduction type doped.

"The substrate may include a lower region and the drift region formed on the lower region. The lower region and the drift region may be doped to the first conduction type and a doping concentration of the drift region may be lower than that of the lower region.

"The lower region of the substrate may be N+-doped, and the drift region may be N-doped.

"The gate may be formed along the side walls of the trench so as to be circular/elliptical-shaped, polygonal ring-shaped, or linear-shaped.

"The gate oxide layer may be formed at an edge of the bottom surface of the trench and along the side walls of the trench so that the central portion of the bottom surface of the trench may be partially exposed.

"The second source region may be partially formed in the central portion of the bottom surface of the trench so as to occupy less than the entire bottom surface of the trench. The gate may overlap the second source region. As a result, an edge of the second source region may face the gate.

"The first source region may be arranged to face an upper portion of a side surface of the gate. The second source region may be arranged under the gate to so as to face the bottom surface of the gate.

"For example, the first and second source regions may be N+-doped.

"The first well region may be formed below the entire first source region. The second well region may entirely surround the bottom surface and the side walls of the second source region.

"A part of the second well region that surrounds the side walls of the second source region may face the bottom surface of the gate.

"For example, the first and second well regions may be P-doped.

"According to an example embodiment, a method of fabricating a semiconductor device may include vertically etching an upper surface of a substrate (which may include a lower region and a drift region on the lower region) to form a trench, the lower region and the drift region of the substrate being doped to a first conduction type, doping the upper surface of the substrate and a bottom surface of the trench to a second conduction type to form a first well region and a second well region, forming a first source region and a second source region on the first well region and the second well region, respectively, the first and second source region being doped to the first conduction type, forming a gate insulating layer at an edge of the bottom surface of the trench and side walls of the trench, and forming a gate on the gate insulating layer at the edge of the bottom surface of the trench and along the side walls of the trench.

"For example, the lower region of the substrate may be N+-doped and the drift region may be N-doped.

"Forming the trench may be performed when an alignment key is formed on a surface of the substrate.

"The method may further include controlling an etching depth so that the bottom surface of the trench is in the drift region.

"Forming the first well region and the second well region may include forming a mask that surrounds the side walls of the trench so that only the central portion of the bottom surface of the trench is exposed and the edge of the bottom surface is covered and doping the upper surface of the substrate to the second conduction type to form the first well region and doping the exposed bottom surface of the trench to the second conduction type to form the second well region.

"Forming the mask may include depositing a mask material on the upper surface of the substrate and the side walls and the bottom surface of the trench and partially leaving the mask material on the side walls of the trench and removing the remaining mask material using anisotropic etching.

"For example, forming the first source region and the second source region may include increasing a thickness of the mask to cover the edge of the second well region with the mask and doping the first well region on the upper surface of the substrate to the first conduction type to form the first source region and doping the exposed portion of the second well region to the first conduction type to form the second source region so that the second well region entirely surrounds the lower surface and the side surfaces of the second source region.

"For example, the first and second source regions may be N+-doped and the first and second well regions may be P-doped.

"The method may further include doping the edge of the first source region and the central portion of the second source region to the second conduction type to form a first ohmic contact layer and a second ohmic contact layer.

"Forming the gate oxide layer and the gate may include forming a gate oxide layer on the upper surface of the substrate and on the side walls and the bottom surface of the trench to a uniform thickness, depositing a gate material along the gate oxide layer, and partially leaving the gate material on the side walls of the trench and removing the remaining gate material to form a gate using anisotropic etching.

"The method may further include forming an interlayer insulating layer on the upper surface of the substrate and on the side walls and the bottom surface of the trench to cover the gate and the gate oxide layer, partially removing the gate oxide layer and the interlayer insulating layer that cover the first and second source regions to expose parts of the first and second source regions, and depositing a conductive material on the upper surface of the substrate and in the trench to form a source electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other features and advantages of the present disclosure will become more apparent upon review of the example embodiments with reference to the attached drawings in which:

"FIG. 1 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to an example embodiment;

"FIG. 2 is a schematic perspective view illustrating a structure of a gate of the semiconductor device illustrated in FIG. 1;

"FIG. 3 is a plan view illustrating an inside of a trench of the semiconductor device illustrated in FIG. 1;

"FIG. 4 is a cross-sectional view schematically illustrating a structure of the semiconductor device of FIG. 3, taken along line B-B'; and

"FIGS. 5A to 5I are cross-sectional views schematically illustrating processes of fabricating the semiconductor device illustrated in FIG. 4."

For additional information on this patent application, see: UM, Chang-yong; SHIN, Jai-kwang. Semiconductor Device Having Dual Parallel Channel Structure and Method of Fabricating the Same. Filed August 6, 2013 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4399&p=88&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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