The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "To be commercially sold in
"The trip response time of a GPCI, and therefore by extension the duration of a simulated test procedure, may depend, at least in part, on the type of ground fault detection integrated circuit or IC employed. There are two types of commonly used ground fault detection ICs available commercially. The first type is available from, e.g., National Semiconductor (e.g., LM 1851) or Fairchild T Semiconductor (e.g., FANl 851), in addition to other alternative vendors. The other type is available from, e.g.,
"The first type of commonly used ground fault detection IC (i.e., the LMl 851, the FANl 851, and the like) is an integrating type circuit and takes advantage of a timing curve specified in UL943 and as a result trips in accordance with the UL943 timing requirements for prescribed fault magnitudes. Use of the timing curve by ground fault detection ICs of this type generally results in a longer response time for smaller magnitude faults and a faster response time for larger magnitude faults. This variable response time is also exhibited by these types of ground fault detection ICs in the presence of simulated faults.
"The other type of commonly used ground fault detection IC (i.e., the RV4141, and the like) which is a comparator circuit do not utilize the UL943 timing curve and instead have a generally small trip response time in the presence of a current level that exceeds a prescribed threshold. The typical trip response time for these types of ground fault detection ICs is 2 ms.
"It is currently being considered to require automatic self testing of fault circuit interrupters."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "One embodiment of the invention relates to a self testing fault circuit interrupter device comprising a fault circuit comprising at least one line monitoring circuit, at least one line interrupting circuit and at least one fault detector circuit which is configured to selectively operate the at least one line interrupting circuit when a fault is detected. This fault circuit also includes at least one test circuit configured to initiate a self test on the fault circuit.
"In at least one embodiment, there is at least one timing circuit for controlling the time period for a self test being performed on the at least one test circuit. The timing circuitry can be in the form of additional circuitry which comprises a transistor which controls the discharge rate of a capacitor.
"In addition, in one embodiment, the testing circuit can include a microcontroller which can be programmed to perform a self test across at least two different half cycles of opposite polarity. The determination of the timing of the self test is based upon timing performed by the microcontroller in combination with zero crossing circuitry.
BRIEF DESCRIPTION OF THE DRAWINGS
"Other objects and features of the present invention will become apparent from the following detailed description considered in connection with the accompanying drawings. It is to be understood, however, that the drawings are designed as an illustration only and not as a definition of the limits of the invention. In the drawings, wherein similar reference characters denote similar elements throughout the several views:
"FIG. 1 is a schematic diagram of a first embodiment of the invention;
"FIG. 2 is a schematic diagram of a second embodiment of the invention;
"FIG. 3 is a schematic diagram of an alternative embodiment to FIGS. 1 and 2;
"FIG. 4A is a graph of different simulated fault signal durations based upon voltage level as function of time;
"FIG. 4B is a graph of a series of events occurring during a self test vs. time;
"FIG. 5 is a flow chart illustrating one embodiment of the process for installing the self test device and conducting a manual test; and
"FIG. 6 is a flow chart illustrating one embodiment of the process for conducting an automatic self test."
For additional information on this patent application, see: OSTROVSKY, Michael; KEVELOS, Adam. Self Testing Fault Circuit Apparatus and Method. Filed
Keywords for this news article include: Electronics, Semiconductor, Microcontroller,
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