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Researchers Submit Patent Application, "Cmos Image Sensor and Method of Manufacturing the Same", for Approval

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor IHARA, Hisanori (Seongnam-si, KR), filed on January 17, 2014, was made available online on July 24, 2014.

The patent's assignee is Samsung Electronics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments relate to a CMOS image sensor and a method of manufacturing the same.

"Recently, semiconductor devices have been highly integrated, and a complementary metal oxide semiconductor (CMOS) image sensor (CIS) has been also highly integrated."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Embodiments are directed to a CMOS image sensor including a photodiode including a first impurity layer and a second impurity layer sequentially formed on a substrate, an isolation layer on the second impurity layer, and a transfer gate structure through the second impurity layer, the transfer gate structure contacting a top surface of the first impurity layer and a portion of the second impurity layer, the transfer gate structure including a bottom surface having a step shape.

"The transfer gate structure may include a gate electrode and a gate dielectric layer beneath the gate electrode.

"The gate electrode may include a lower portion, a central portion, and an upper portion thereof. The lower portion of the gate electrode may contact the top surface of the first impurity layer via the gate dielectric layer. The central portion of the gate electrode may contact a portion of the second impurity layer via the gate dielectric layer. The upper portion of the gate electrode may contact a top surface of the second impurity layer and a top surface of the isolation layer via the gate dielectric layer.

"A portion of the lower portion of the gate electrode may be in a non-overlapping relationship with the upper portion of the gate electrode, when viewed from a top side.

"A portion of the central portion of the gate electrode may be in a non-overlapping relationship with the upper portion of the gate electrode, when viewed from a top side.

"The first impurity layer and the second impurity layer may include different conductivity type impurities from each other.

"Embodiments are also directed to a method of manufacturing a CMOS image sensor including sequentially forming a first impurity layer and second impurity layer on a substrate, forming an isolation layer on the second impurity layer, and forming a transfer gate structure through the second impurity layer, the transfer gate structure contacting a top surface of the first impurity layer and a portion of the second impurity layer, the transfer gate structure including a bottom surface having a step shape.

"Forming the transfer gate structure may include forming a gate dielectric layer and a gate electrode sequentially stacked.

"Forming the gate electrode may include forming a lower portion, a central portion, and an upper portion thereof.

"Forming the gate dielectric layer and the gate electrode sequentially stacked may include removing a portion of the second impurity layer to expose the top surface of the first impurity layer, forming the gate dielectric layer on the exposed top surface of the first impurity layer and on the second impurity layer, and forming the gate electrode on the gate dielectric layer. The gate dielectric layer may be further formed on the isolation layer.

"The first impurity layer and the second impurity layer may be formed to include different conductivity type impurities from each other, and form a photodiode.

"Embodiments are also directed to a CMOS image sensor including a first impurity layer, a second impurity layer on the first layer, the first impurity layer and the second impurity layer forming a photodiode, an isolation layer on the second impurity layer, portions of the second impurity layer and the isolation layer being absent above the first impurity layer such that a portion of the first impurity layer is exposed and such that the second impurity layer includes steps between the exposed first impurity layer and a top surface of the second impurity layer, and a transfer gate structure extending through the second impurity layer, the transfer gate structure contacting the exposed top surface of the first impurity layer and the steps of the second impurity layer, the transfer gate structure including a bottom surface having a step shape complementary to the steps of the second impurity layer.

"The transfer gate structure may include a gate electrode and a gate dielectric layer beneath the gate electrode.

"A lower portion of the transfer gate structure may contact the top surface of the first impurity layer. A central portion of the transfer gate structure may contact the steps of the second impurity layer. An upper portion of the transfer gate structure may contact a top surface of the second impurity layer and a top surface of the isolation layer.

"A portion of the upper portion of the transfer gate structure may not overlap part of the lower portion and central portion of the transfer gate structure, when viewed from a top side.

"The CMOS image sensor may further include an insulation layer covering the transfer gate structure and exposed portions of the isolation layer.

"The first impurity layer and the second impurity layer may include different conductivity type impurities from each other.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

"FIG. 1 illustrates a plan view depicting a unit cell of a CIS in accordance with example embodiments, and

"FIG. 2 illustrates a cross-sectional view cut along a line A-A' of FIG. 1;

"FIGS. 3 to 7 illustrate cross-sectional views depicting stages of a method of manufacturing a CIS in accordance with example embodiments; and

"FIGS. 8 to 13 illustrate cross-sectional views depicting stages of a method of manufacturing a CIS in accordance with example embodiments."

For additional information on this patent application, see: IHARA, Hisanori. Cmos Image Sensor and Method of Manufacturing the Same. Filed January 17, 2014 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4414&p=89&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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