News Column

Patent Issued for Wiring Substrate and Semiconductor Package

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Fujii, Tomoharu (Nagano, JP), filed on August 24, 2012, was published online on July 22, 2014.

The assignee for this patent, patent number 8786099, is Shinko Electric Industries Co., Ltd. (Nagano-Shi, JP).

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a wiring substrate made of an inorganic material and a semiconductor package in which a semiconductor chip is mounted on the wiring substrate.

"Wiring substrates made of organic materials such as insulative resins and wiring substrates made of inorganic materials such as silicon are known. In wiring substrates made of organic materials, a planar power plane and ground (GND) plane are formed to attain impedance matching, reduction of power source impedance, etc., as disclosed in JP-A-2001-148448.

"The resistance of a power pattern or a ground pattern can be made low by making the area of a power plane or a GND plane as wide as possible. When opposed to each other at a small interval, a power plane and a GND plane can be made more capacitive than inductive. Furthermore, impedance matching can be attained by interposing a signal electrode between a power plane and a GND plane.

"On the other hand, in wiring substrates made of inorganic materials, because of a microloading effect etc., it is difficult to form a planar power plane or GND plane. Therefore, a power line and a GND line are each formed merely by very fine wiring patterns and a via line.

"Besides, the microloading effect is a phenomenon that the etching rate varies depending on the aspect ratio (i.e., the ratio between the width and the depth) of a pattern.

"However, if a power line and a GND line are each formed merely by very fine wiring patterns and a via line in a wiring substrate made of an inorganic material, layers having wide conductor areas cannot be secured, as a result of which the power line and the GND line are made large in resistance and become more capacitive than inductive. As a result, power source impedance is made high. Furthermore, impedance matching with a line for high-speed input/output signals cannot be attained.

"Even if the structure disclosed in JP-A-2001-148448 is employed, it is not easy to attain impedance matching though low power source impedance can be attained."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "The present invention has been made in view of the above, and an object of the invention is therefore to provide a wiring substrate which can attain low power source impedance and impedance matching easily though made of an inorganic material, as well as a semiconductor package in which a semiconductor chip is mounted on such a wiring substrate.

"A wiring substrate according to the invention includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode. The first electrode portion may include a plurality of first electrodes, the second electrode portion may include a plurality of second electrodes, and the first electrodes and the second electrodes may be arranged alternately at prescribed intervals in each of a first direction and a second direction which are perpendicular to each other.

"The above-disclosed technique makes it possible to provide a wiring substrate which can attain low power source impedance and impedance matching easily though made of an inorganic material, as well as a semiconductor package in which a semiconductor chip is mounted on such a wiring substrate."

For more information, see this patent: Fujii, Tomoharu. Wiring Substrate and Semiconductor Package. U.S. Patent Number 8786099, filed August 24, 2012, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8786099.PN.&OS=PN/8786099RS=PN/8786099

Keywords for this news article include: Electronics, Semiconductor, Shinko Electric Industries Co. Ltd.

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Source: Electronics Newsweekly


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