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Patent Issued for Three Dimensional Microelectronic Components and Fabrication Methods for Same

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventor Karpman, Maurice (Brookline, MA), filed on June 5, 2012, was published online on July 22, 2014.

The patent's assignee for patent number 8785249 is The Charles Stark Draper Laboratory, Inc. (Cambridge, MA).

News editors obtained the following quote from the background information supplied by the inventors: "Conventional microelectronics fabrication techniques often involve the fabrication of devices, for example microprocessors, on a semiconductor substrate by the selective doping of regions of the substrate and deposition and patterning of various layers of dielectric, metals, and semiconductor materials. These layers of materials are often very thin, on the order of microns. The resulting devices are effectively two dimensional. Providing additional functionality, for example, by the addition of additional transistors or other features to a device, conventionally requires the surface area of the device to be increased, subsequently reducing the number of devices that can be formed on a single wafer or included within a package of a given size."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Aspects and embodiments of the present invention are directed generally to structures used in the fabrication of microelectronic circuits such as integrated circuits, multi-chip modules, and multi-layer high density multi-component modules.

"In accordance with an aspect of the present invention there is provided a method of forming an electrical component. The method comprises selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on one of a bottom surface of the substrate and a dielectric layer formed over the pattern of the first conductive material, dicing the substrate into plurality of dies each having a first diced surface and a second diced surface, securing the first diced surface of each of the plurality of dies to a retaining material, encapsulating the plurality of dies in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surfaces by metalizing a surface of the reconstituted wafer.

"In accordance with some embodiments each of the first conductive material, the second conductive material, and the third conductive materials comprise a metal.

"In accordance with some embodiments forming the pattern of a first conductive material on the top surface of the substrate comprises forming a first plurality of metal lines on the top surface of the substrate

"In accordance with some embodiments forming the pattern of the second conductive material on the bottom surface of the substrate comprises forming a second plurality of metal lines on the bottom surface of the substrate.

"In accordance with some embodiments forming the second plurality of metal lines on the bottom surface of the substrate comprises forming the second plurality of metal lines at positions horizontally displaced from the first plurality of metal lines on the top surface of the substrate.

"In accordance with some embodiments selecting a substrate comprises selecting a substrate comprising a ferrite material.

"In accordance with some embodiments the method further comprises forming a pattern of a fourth conductive material on the first diced surfaces.

"In accordance with some embodiments the method further comprises thinning the reconstituted wafer prior to one of forming the pattern of the third conductive material on the second diced surface and forming the pattern of the fourth conductive material on the first diced surface.

"In accordance with some embodiments forming the pattern of the third conductive material on the second diced surface electrically connects a first metal line on the top side of the substrate to a second metal line on the bottom side of the substrate.

"In accordance with some embodiments forming the pattern of the fourth conductive material on the first diced surface electrically connects a fourth metal line on the top side of the substrate to the second metal line on the bottom side of the substrate.

"In accordance with some embodiments the electrical component formed comprises an inductor.

"In accordance with some embodiments selecting a substrate comprises selecting a substrate comprising an insulating material.

"In accordance with some embodiments the method further comprises forming one or more bond pads in electrical communication with one or more of the first plurality of metal lines on an upper side of the reconstituted wafer.

"In accordance with some embodiments the method further comprises forming one or more bond pads in electrical communication with one or more of the first plurality of metal lines on a lower side of the reconstituted wafer.

"In accordance with some embodiments the method further comprises thinning the reconstituted wafer prior to one of forming the one or more bond pads on the upper side of the reconstituted wafer and forming the one or more bond pads on the lower side of the reconstituted wafer.

"In accordance with some embodiments the method further comprises incorporating the electrical component into an electronic module, one of the first plurality of metal lines configured as a through wafer via in the electronic module and electrically connecting a second electronic component in the electronic module to the one of the first plurality of metal lines.

"In accordance with some embodiments the one or more of the first plurality of metal lines have a length in a direction normal to the first diced surface of greater than about 1 mm.

"In accordance with some embodiments the one or more of the first plurality of metal lines have a length which is greater than about 15 times a thickness of the one or more of the first plurality of metal lines and about 15 times a width of the one or more of the first plurality of metal lines.

"In accordance with another aspect of the present invention there is provided a method of forming an electrical component. The method comprises forming a first pattern of metal lines on a top surface of a substrate, each of the metal lines in the first pattern having a length, forming a second pattern of a metal lines on one of a bottom surface of the substrate and a dielectric layer formed over the pattern of the first conductive material, the metal lines in the second pattern parallel to the metal lines in the first pattern, dicing the substrate into one or more die having a first diced surface and a second diced surface, and forming a third pattern of metal on the first diced surface.

"In accordance with some embodiments forming the second pattern of a metal lines comprises forming the second pattern of a metal lines horizontally displaced from the metal lines in the first pattern in a direction normal to a direction defined by the length of a metal line in the first pattern of metal lines and in a plane parallel to the bottom surface of the substrate.

"In accordance with some embodiments forming the third pattern of metal comprises forming a third pattern of metal lines.

"In accordance with some embodiments the method further comprises forming a fourth pattern of metal lines on the second diced surface.

"In accordance with some embodiments the method further comprises electrically connecting a metal line in the first pattern of metal lines and a metal line in the second pattern of metal lines with a metal line in one of the third pattern of metal lines and the fourth pattern of metal lines.

"In accordance with another aspect of the present invention there is provided a method of forming an electrical component. The method comprises selecting a substrate, forming a layer of first sacrificial material on a top surface of the substrate, forming a pattern of a first conductive material on a top surface of the layer of the first sacrificial material, forming a layer of second sacrificial material on a top surface of the pattern of the first conductive material, forming a pattern of a second conductive material on a top surface of the layer of the second sacrificial material, forming an end structure physically joined to at least a portion of the pattern of the first conductive material and to at least a portion of the pattern of the second conductive material; removing the substrate and the layer of the first sacrificial material from the pattern of the first conductive material, embedding the pattern of the first conductive material and the pattern of the second conductive material in one of a reconstituted wafer and a multi-chip module, and removing the end structure from the embedded pattern of the first conductive material and pattern of the second conductive material."

For additional information on this patent, see: Karpman, Maurice. Three Dimensional Microelectronic Components and Fabrication Methods for Same. U.S. Patent Number 8785249, filed June 5, 2012, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8785249.PN.&OS=PN/8785249RS=PN/8785249

Keywords for this news article include: Semiconductor, Microelectronics, Electrical Communication, The Charles Stark Draper Laboratory Inc.

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Source: Electronics Newsweekly


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