The patent's inventors are Lim,
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "In each new generation of semiconductor processing, a variety of changes are observed, such as, increasing processing and tooling costs, increasing design, verification and testing costs, and increasing development and deployment time. The rate of these changes is greater than the rate of change of the input/output (I/O) requirements of the devices. In addition, the improved logic and memory area reduction that each new process generation provides does not scale equally with circuits that include I/O and non-logic structures, such as, for example, analog, phase locked loop (PLL), voltage regulator, and electro static discharge (ESD) structures, because these circuits use thick oxide transistors. Many semiconductor devices become bound by the I/O of a die, and the logic and memory density in each new process is sometimes limited by the number of I/Os."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "Embodiments of the present invention relate to an I/O stack and systems and methods for its fabrication. The methods include stacking an I/O die including I/O elements and excluding a logic element. The methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which more logic elements are fitted within the same surface area on a substrate of the integrated circuit die.
"In various embodiments, the number of logic elements on the integrated circuit die may be greater than the number of I/O elements on the integrated circuit die. Moreover, the number of I/O elements on the I/O die may be greater than the number of logic elements on the I/O die.
"In one aspect, a method for fabricating an I/O stack is provided. One embodiment of the method includes stacking an I/O die including a first set of elements with respect to an integrated circuit die. The integrated circuit includes a second set of elements other than an I/O element. The elements of the first set are other than a logic element. Moreover, the first set of elements includes a plurality of I/O elements and the second set of elements includes a plurality of logic elements.
"In another aspect, an I/O stack is provided. In one embodiment, the I/O stack includes an I/O die and an integrated circuit die that is stacked with respect to the I/O die. The I/O die includes multiple I/O elements and excludes a logic element and the integrated circuit die includes multiple logic elements and excludes an I/O element.
"The separation of the I/O die from the integrated circuit die allows for reusing the I/O dies with other integrated circuits, including an upgraded integrated circuit. Moreover, the separation allows for more I/O elements to be fitted on the I/O die than that fitted in a conventional die for the same amount of logic elements of the integrated circuit die."
For the URL and additional information on this patent, see: Lim,
Keywords for this news article include: Electronics, Semiconductor,
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