News Column

Patent Issued for Structure for Integrated Circuit Alignment

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Harn, Yu-Chyi (Bao-Shan, TW); Wang, Sophia (Xin-Zhu, TW); Lin, Chun-Hung (Taoyuan, TW); Chen, Hsien-Wei (Sinying, TW); Chiu, Ming-Yen (Hsinchu, TW), filed on November 16, 2009, was published online on July 22, 2014.

The assignee for this patent, patent number 8786054, is Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu, TW).

Reporters obtained the following quote from the background information supplied by the inventors: "The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. Conventionally, semiconductor devices are fabricated by patterning a sequence of patterned and un-patterned layers, and the features on successive patterned layers are spatially related to each other. During the fabrication, each patterned layer must be aligned with the previous patterned layers with a degree of precision. Pattern alignment techniques typically provide alignment marks to achieve overall exposure field alignment. As technology nodes continue to decrease, it has been observed that such alignment techniques provide less than desirable alignment within the field."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The present disclosure provides for many different embodiments. An exemplary semiconductor wafer is provided. The semiconductor wafer comprises an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.

"An exemplary method is also provided. The method may provide improved alignment of in-chip/die features. The method includes providing a semiconductor wafer; defining a field on the semiconductor wafer, wherein a perimeter of the field is defined by a scribe line; and defining a die area within the field, wherein a perimeter of the die is defined by a scribe line. Alignment marks are formed within the scribe line defining the perimeter of the field and in a corner portion of the die area."

For more information, see this patent: Harn, Yu-Chyi; Wang, Sophia; Lin, Chun-Hung; Chen, Hsien-Wei; Chiu, Ming-Yen. Structure for Integrated Circuit Alignment. U.S. Patent Number 8786054, filed November 16, 2009, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8786054.PN.&OS=PN/8786054RS=PN/8786054

Keywords for this news article include: Electronics, Taiwan Semiconductor Manufacturing Company Ltd.

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Source: Electronics Newsweekly


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