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Patent Issued for Signal Input Circuit and Semiconductor Device Having the Same

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventor Koo, Kyunghoi (Suwon-si, KR), filed on July 29, 2010, was published online on July 22, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8786320 is assigned to Samsung Electronics Co., Ltd. (KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present inventive concept relates to a signal input circuit included in a semiconductor device.

"A signal input circuit that is connected to the input unit of a device may be implemented with a differential input circuit or a single-ended input circuit according to requirements. The single-ended input circuit is a circuit structure in which an input signal is applied or an output signal is outputted through only the one end of a pair of ports in an electric circuit. The differential input circuit has a circuit structure in which an input signal is applied or an output signal is outputted through the both ends of a pair of ports. The differential input circuit may be designed to have a scheme of amplifying and outputting the voltage difference between two complementary signals or a scheme of amplifying and outputting the difference between an input signal and a reference signal.

"A signal input circuit should be configured with one of the differential input signal and the single-ended input circuit according to the transmission scheme of a circuit for transmitting a data signal. If the signal input circuit is designed so as to receive a differential signal and a single signal, the range of applications of the signal input circuit may become larger."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "The present disclosure provides a signal input circuit, which has a simple circuit configuration and can receive a differential signal and a single signal.

"According to one aspect, the inventive concept is directed to a signal input circuit including: an input unit receiving a first input signal to output an output signal to an output node; a first compensation circuit connected to the output node, discharging the output node in response to a second input signal; a second compensation circuit connected to the output node, supplying a current to the output node in response to the second input signal; and an enable circuit enabling the input unit and the first and second compensation circuits in response to at least one operation mode selection signal.

"In some embodiments, the input unit may include: a PMOS transistor connected between a power source voltage terminal and the output node, and controlled by the first input signal; and an NMOS transistor connected between the output node and the enable circuit, and controlled by the first input signal.

"In some embodiments, the first compensation circuit may include: a PMOS transistor connected between a power source voltage terminal and a first node, and controlled by the second input signal; a first NMOS transistor connected between the first node and the enable circuit, and controlled by a signal of the first node; and a second NMOS transistor connected between the output node and the enable circuit, and controlled by the signal of the first node.

"In some embodiments, the second compensation circuit may include: a first PMOS transistor connected between a power source voltage terminal and the output node, and controlled by a signal of a second node; a second PMOS transistor connected between the power source voltage terminal and the second node, and controlled by the signal of the second node; and an NMOS transistor connected between the second node and the enable circuit, and controlled by the second input signal.

"In some embodiments, the first and second input signals may be inverted therebetween.

"In some embodiments, the enable circuit may receive first and second operation mode selection signals, enable the first and second compensation circuits in response to the first operation mode selection signal, and enable the input unit in response to the second operation mode selection signal.

"According to another aspect, the inventive concept is directed to a signal input circuit which includes: an input unit receiving a first input signal to output an output signal to an output node; a first compensation circuit connected to the output node, discharging the output node in response to a second input signal; a second compensation circuit connected to the output node, supplying a current to the output node in response to the second input signal; and a switching circuit respectively connected to the input unit, the first compensation circuit and the second compensation circuit through first to third connection nodes, connecting the first to third connection nodes to a ground voltage terminal in response to at least one operation mode selection signal.

"In some embodiments, the input unit comprises: a PMOS transistor connected between a power source voltage terminal and the output node, and controlled by the first input signal; and an NMOS transistor connected between the output node and the switching circuit, and controlled by the first input signal.

"In some embodiments, the first compensation circuit comprises: a PMOS transistor connected between a power source voltage terminal and a first node, and controlled by the second input signal; a first NMOS transistor connected between the first node and the first connection node of the switching circuit, and controlled by a signal of the first node; and a second NMOS transistor connected between the output node and the first connection node of the switching circuit, and controlled by the signal of the first node.

"In some embodiments, the second compensation circuit comprises: a first PMOS transistor connected between a power source voltage terminal and the output node, and controlled by a signal of the second node; a second PMOS transistor connected between the power source voltage terminal and the second node, and controlled by the signal of the second node; and an NMOS transistor connected between the second node and the second connection node of the switching circuit, and controlled by the second input signal.

"In some embodiments, the first and second input signals are inverted therebetween.

"In some embodiments, the switching circuit receives first and second operation mode selection signals, connects the second and third connection nodes which are respectively connected to the first and second compensation circuits to the ground voltage terminal, and connects the first connection node connected to the input unit to the ground voltage terminal in response to the second operation mode selection signal.

"In some embodiments, the switching circuit comprises: a first NMOS transistor connected between the ground voltage terminal and the first connection node which is connected to the input unit, and controlled by the first operation mode selection signal; a second NMOS transistor connected between the ground voltage terminal and the second connection node which is connected to the first compensation circuit, and controlled by the second operation mode selection signal; and a third NMOS transistor connected between the ground voltage terminal and the third connection node which is connected to the second compensation circuit, and controlled by the second operation mode selection signal.

"According to another aspect, the inventive concept is directed to a signal input circuit which includes: a PMOS transistor connected between a power source voltage terminal and an output node, and controlled by a first input signal; an NMOS transistor connected between the output node and a switching circuit, and controlled by the first input signal; a first compensation circuit connected to the output node, compensating an operation delay of the PMOS transistor in response to a second input signal; a second compensation circuit connected to the output node, compensating an operation delay of the NMOS transistor in response to the second input signal; and an enable circuit enabling the PMOS transistor, the NMOS transistor and the first and second compensation circuits in response to at least one operation mode selection signal.

"In some embodiments, the first and second input signals may be inverted therebetween.

"In some embodiments, the first compensation circuit discharges the output node when the second input signal has a first level, and the second compensation circuit supplies a current to the output node when the second input signal has a second level.

"According to another aspect, the inventive concept is directed to a semiconductor device which includes: a first circuit; and a second circuit receiving a data signal from the first circuit, and including a signal input circuit for receiving the data signal from the first circuit, wherein the signal input circuit includes: an input unit receiving a first input signal to output an output signal to an output node; a first compensation circuit connected to the output node, discharging the output node in response to a second input signal; a second compensation circuit connected to the output node, supplying a current to the output node in response to the second input signal; and an enable circuit enabling the input unit and the first and second compensation circuits in response to at least one operation mode selection signal.

"In some embodiments, the first and second input signals are inverted therebetween, and the enable circuit receives first and second operation mode selection signals, enables the first and second compensation circuits in response to the first operation mode selection signal, and enables the input unit in response to the second operation mode selection signal.

"In some embodiments, the first compensation circuit comprises: a PMOS transistor connected between a power source voltage terminal and a first node, and controlled by the second input signal; a first NMOS transistor connected between the first node and the first connection node of the switching circuit, and controlled by a signal of the first node; and a second NMOS transistor connected between the output node and the first connection node of the switching circuit, and controlled by the signal of the first node, and the second compensation circuit comprises: a first PMOS transistor connected between a power source voltage terminal and the output node, and controlled by a signal of the second node; a second PMOS transistor connected between the power source voltage terminal and the second node, and controlled by the signal of the second node; and an NMOS transistor connected between the second node and the second connection node of the switching circuit, and controlled by the second input signal."

URL and more information on this patent, see: Koo, Kyunghoi. Signal Input Circuit and Semiconductor Device Having the Same. U.S. Patent Number 8786320, filed July 29, 2010, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8786320.PN.&OS=PN/8786320RS=PN/8786320

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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