News Column

Patent Issued for Semiconductor Integrated Circuit Device

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Rohm Co., Ltd. (Kyoto, JP) has been issued patent number 8786092, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Okazaki, Mitsuru (Kyoto, JP); Kajiwara, Youichi (Kyoto, JP); Takahashi, Naoki (Kyoto, JP); Shimizu, Akira (Kyoto, JP).

This patent was filed on September 22, 2011 and was published online on July 22, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of the reliability thereof in a temperature cycle test.

"A temperature cycle test is conventionally imposed as one type of reliability evaluation test on semiconductor integrated circuit devices in which high reliability is required in varying use environments (e.g., a serial control LED (light emitting diode) driver for automobiles). A temperature cycle test is a test in which a semiconductor integrated circuit device is tested for reliability by being exposed alternately to a high and a low temperature (e.g., +150.degree. C. and -65.degree. C.) repeatedly at predetermined intervals.

"When a conventional semiconductor integrated circuit device is subjected to the temperature cycle test as described above, thermal stress resulting from differences in thermal expansion coefficient among an element forming region, a metal wiring layer, and a passivation layer may produce a crack (exfoliation) in the passivation layer, causing even the metal wiring layer right under the passivation layer to exfoliate together in the worst case. This leads to degraded reliability and reduced yields. In particular, elongate chips such as display drivers and sensors are liable to be seriously affected.

"As a solution to the above described problem, a semiconductor integrated circuit device has conventionally been disclosed and proposed in which a metal wiring layer and a passivation layer have elevations and depressions (slits) formed thereon (see JP-A-H05-283540, hereinafter referred to as Patent Literature 1).

"As another conventional art related to the present invention, a semiconductor chip in which a dummy pattern is formed between an identification area including an identification mark and a dicing line has been disclosed and proposed (see JP-A-H05-251556 filed by the applicant of the present application, hereinafter referred to as Patent Literature 2).

"With the conventional art of Patent Literature 1, it is indeed possible to disperse thermal stress to prevent development of cracks in the passivation layer. However, the conventional art of Patent Literature 1 is disadvantageous in that it requires an extra process for forming elevations and depressions on the metal wiring layer and the passivation layer (more specifically, a process for forming elevations and depressions on an interlayer insulating film laid immediately under the metal wiring layer), and this invites reduced productivity and yields.

"The conventional art of Patent Literature 2 simply aims at reducing exfoliation during the dicing of a semiconductor chip and the resulting identification errors. Thus, it in no way helps prevent development of cracks in a passivation layer during a temperature cycle test."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An object of the present invention is to provide a highly reliable semiconductor integrated circuit device.

"To achieve the above object, according to the present invention, a semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

"Other features, elements, steps, advantages and characteristics of the present invention will become more apparent from the following detailed description of preferred embodiments thereof with reference to the attached drawings."

For the URL and additional information on this patent, see: Okazaki, Mitsuru; Kajiwara, Youichi; Takahashi, Naoki; Shimizu, Akira. Semiconductor Integrated Circuit Device. U.S. Patent Number 8786092, filed September 22, 2011, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8786092.PN.&OS=PN/8786092RS=PN/8786092

Keywords for this news article include: Electronics, Rohm Co. Ltd., Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters