News Column

Patent Issued for Semiconductor Device Having Vertical Channel Transistor and Methods of Fabricating the Same

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Chung, Hyung-woo (Seoul, KR); Oh, Yong-chul (Suwon-si, KR); Hwang, Yoo-sang (Suwon-si, KR); Jin, Gyo-young (Seoul, KR); Hong, Hyeong-sun (Seongnam-si, KR); Kim, Dae-ik (Yongin-si, KR), filed on December 21, 2012, was published online on July 22, 2014.

The assignee for this patent, patent number 8785998, is Samsung Electronics Co., Ltd. (Suwon-si, Gyeonggi-do, KR).

Reporters obtained the following quote from the background information supplied by the inventors: "The inventive concept relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device including a vertical channel transistor, and a method of fabricating the semiconductor device.

"As the integration of semiconductor devices increases, the design rules for components in the semiconductor devices decrease. In particular, in a semiconductor device having a plurality of transistors, a gate length has been reduced. The gate length is a reference of the design rules. Accordingly, a length of the channel in each transistor has also been reduced. A vertical channel transistor may increase a distance between a source region and a drain region, and may increase a length of an effective channel in a transistor."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The inventive concept provides a semiconductor device having a vertical channel transistor. According to an embodiment, a vertical channel region in the vertical channel transistor may not be disturbed by a bias even when a high bias voltage is applied to bit lines. The vertical channel can be formed in an active area facing a sidewall of a contact gate.

"The inventive concept also provides a method of fabricating a semiconductor device having a vertical channel transistor, and arranging contact gates and bit lines so that the vertical channel region is not disturbed by a bias even when a high bias voltage is applied to the bit lines.

"According to an embodiment, a semiconductor memory device comprises a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

"A distance from an upper surface of the substrate to a bottom surface of the first contact gate can be less than a distance from the upper surface of the substrate to an upper surface of the first bit line.

"The first pair of pillars and the substrate may comprise a semiconductor material.

"The device may further comprise a nitride liner, a sidewall oxide layer, and a gap fill oxide layer respectively stacked on a sidewall of the first trench.

"A first source/drain region can be formed around the bottom surface of the first trench.

"Each end portion of the pair of pillars may comprise a second source/drain region.

"The device may further comprise a first contact plug and a second contact plug respectively disposed on each end portion of the first pillar and the second pillar.

"A lower electrode of a capacitor can be disposed on the first contact plug.

"The device may further comprise a spacer disposed between the first contact plug and the first contact gate.

"The spacer can have a ring shape.

"A channel region can be formed between the first source/drain region and the second source/drain region.

"The device may further comprise a second bit line disposed in a second trench formed between the first pair of pillars and a second pair of pillars formed immediately next to the first pair of pillars in the first direction.

"The first and second bit lines may comprise at least one of W, Al, Cu, Mo, Ti, Ta, Ru, TiN, TiN/W, Ti/TiN, WN, W/WN, TaN, Ta/TaN, TiSiN, TaSiN, WSiN, CoSi.sub.2, TiSi.sub.2, or WSi.sub.2.

"The device may further comprise a third insulating layer disposed between the first word line and the second word line.

"The first bit line may comprise a first portion disposed between the first pair of pillars and a second portion disposed between a third pair of pillars neighboring immediately next to the first pair of pillars in the second direction, the first portion in contact with the bottom surface of the first trench comprising a semiconductor material, the second portion in contact with the bottom surface of the second trench comprising an insulating material.

"The first portion and the second portion may have a same width.

"The first portion and the second portion may have a same thickness.

"An upper surface of the first portion of the first bit line can be coplanar with an upper surface of the second portion of the first bit line.

"The first portion can have a smaller thickness than the second portion.

"A top width of the second portion of the first bit line can be wider than a bottom width of the second portion of the first bit line.

"A lower portion of the second portion of the first bit line can be narrower than a lower portion of the first portion of the first bit line.

"A curvature of a lower end of the second portion can be greater than a curvature of a lower end of the first portion.

"A width of the first portion can be smaller than a width of the second portion.

"Each of the pillars can have a same width.

"According to an embodiment, a semiconductor memory device comprise a plurality of pillars extending from a substrate to form vertical channel regions, a word line disposed between two adjacent rows of the pillars, a bit line disposed between two adjacent columns of the pillars, the bit line in contact with a bottom surface of a first trench formed between a first pair of pillars positioned in a row direction, the first pair of pillars having a first pillar and a second pillar, and a contact gate disposed between a second pair of pillars positioned in a column direction, the second pair of pillars having the second pillar and a third pillar, the contact gate comprising a first surface and a second surface, the first surface in contact with the word line, the second surface in contact with a gate insulating layer disposed on the second pillar.

"A distance from an upper surface of the substrate to a bottom surface of the contact gate can be less than a distance from the upper surface of the substrate to an upper surface of the bit line.

"The first pair of pillars and the substrate may comprise a semiconductor material.

"The device may further comprise a nitride liner, a sidewall oxide layer, and a gap fill oxide layer respectively stacked on a sidewall of the first trench.

"The device may further comprise a first source/drain region formed around the bottom surface of the first trench.

"Each end portion of the first pair of pillars may comprise a second source/drain region.

"The device may further comprise a first contact plug and a second contact plug respectively disposed on each end portion of the first pillar and the second pillar.

"A lower electrode of a capacitor can be disposed on the first contact plug.

"The device may further comprise a spacer disposed between the first contact plug and the first contact gate.

"The spacer can have a ring shape.

"A channel region can be formed between the first source/drain region and the second source/drain region.

"The bit line may comprise a first portion disposed between the first pair of pillars and a second portion disposed between a third pair of pillars neighboring immediately next to the first pair of pillars in the column direction, the first portion in contact with the bottom surface of the first trench comprising a semiconductor material, the second portion in contact with the bottom surface of a second trench comprising an insulating material.

"The first portion and the second portion can have a same width.

"The first portion and the second portion can have a same thickness.

"An upper surface of the first portion can be coplanar with an upper surface of the second portion.

"The first portion can have a smaller thickness than the second portion.

"A top width of the second portion can be wider than a bottom width of the second portion.

"A lower portion of the second portion can be narrower than a lower portion of the first portion.

"A curvature of a lower end of the second portion can be greater than a curvature of a lower end of the first portion.

"A width of the first portion can be smaller than a width of the second portion.

"Each of the pillars can have a same width.

"The bit line may comprise at least one of W, Al, Cu, Mo, Ti, Ta, Ru, TiN, TiN/W, Ti/TiN, WN, W/WN, TaN, Ta/TaN, TiSiN, TaSiN, WSiN, CoSi.sub.2, TiSi.sub.2, or WSi.sub.2.

"According to an embodiment, a semiconductor memory device comprise a first semiconductor pillar and a second semiconductor pillar both extending from a semiconductor substrate, a first source/drain region disposed at near a diverged portion of the two pillars, a second source/drain region disposed at near respective top end portions of the two pillars, a first gate insulating layer disposed on a first surface of the first semiconductor pillar and a second gate insulating layer disposed on a second surface of the second semiconductor pillar, the first surface and the second surface face opposite directions, a buried bit line disposed on and in contact with the diverged portion of the two pillars, a first gate contact disposed on the first gate insulating layer and a second gate contact disposed on the second gate insulating layer, and a first word line disposed on and in contact with the first gate contact and a second word line disposed on and in contact with the second gate contact, wherein channels are formed between the first source/drain region and second source drain regions when the first and second contact gates are turned on.

"A distance from an upper surface of the substrate to a bottom surface of the first contact gate can be less than a distance from the upper surface of the substrate to an upper surface of the buried bit line.

"The first source/drain region may comprise a low concentration dopant region and a high concentration dopant region.

"A portion of the buried bit line corresponding to the diverged portion may have a different shape as compared to another portion of the buried bit line corresponding to a portion other than the diverged portion.

"The first word line and the first gate contact can be formed of a unitary structure.

"The buried bit line comprises at least one of W, Al, Cu, Mo, Ti, Ta, Ru, TiN, TiN/W,

"Ti/TiN, WN, W/WN, TaN, Ta/TaN, TiSiN, TaSiN, WSiN, CoSi.sub.2, TiSi.sub.2, or WSi.sub.2.

"According to an embodiment, a method of forming a semiconductor memory device comprises forming a device isolation layer in a semiconductor substrate, the device isolation

"layer isolating a first active region from a second active region, the first active region and the second active region disposed in a first direction, forming a first trench crossing the first active region thereby forming a first pillar and a second pillar, forming a second trench crossing the device isolation layer, the second trench disposed immediately next to the first trench in the first direction, forming a first source/drain region near a bottom surface of the first trench at the first active region, forming a second source/drain region near respective top ends of the first and second pillars, forming a first bit line on a bottom surface of the first trench and forming a second bit line on a bottom surface of the second trench, forming a contact gate disposed between the first bit line and the second bit line, a first surface of the contact gate contacting a gate insulating layer disposed on the first pillar, and forming a word line in contact with a second surface of the contact gate, the word line extending in the first direction.

"Forming the device isolation layer may comprise forming a side wall oxide layer covering an inner wall of a trench in the semiconductor substrate, forming a nitride liner on the side wall oxide layer, and forming a gap fill oxide layer on the nitride liner to fill the inside of the trench.

"Forming the first trench and the second trench may comprise anisotropically etching the semiconductor substrate and the device isolation layer using mask pattern.

"Forming a first/source drain region may comprise performing ion implantation of a low concentration dopant into the semiconductor substrate, and performing ion implantation of a high concentration dopant into the semiconductor substrate.

"Forming the first bit line may comprise forming a conductive layer in the first and second trenches, and performing an etch back process so that the conductive layer to be remained only on the bottom surfaces of the first and second trenches.

"The method may further comprise depositing a buried insulating material on the first and second bit lines to fill inner surfaces of the first and second trenches.

"The buried insulating material may comprise a silicon nitride layer.

"The method may further comprise forming a contact recess between the first bit line and the second bit line to receive the contact gate, and forming a gate insulating layer in an inner wall of the contact recess.

"A process of forming the gate insulating layer may comprise at least one of a radical oxidation process, a thermal oxidation process, a CVD process, or an atomic layer deposition process.

"According to an embodiment, a semiconductor device comprises an active area defined in a substrate to have a longer axis length in a first direction and a shorter axis length in a second direction that is perpendicular to the first direction, and including two active pillars that are separated from each other on an upper surface of the substrate, a buried bit line crossing the active area through a space between the two active pillars and extending in the second direction at a level lower than the upper surface of the substrate, a first source/drain region formed around a bottom surface of the buried bit line in the active area, second source/drain regions formed on upper surfaces of the two active pillars, a gate insulating layer covering vertical side surfaces of the active pillars, which provide channel surfaces on which vertical channels are formed between the first source/drain region and the second source/drain region, contact gates facing the vertical side surfaces of the active pillars with the gate insulating layer disposed between the contact gates and the active pillars, and a word line connected to the contact gates and formed on the upper surface of the substrate."

For more information, see this patent: Chung, Hyung-woo; Oh, Yong-chul; Hwang, Yoo-sang; Jin, Gyo-young; Hong, Hyeong-sun; Kim, Dae-ik. Semiconductor Device Having Vertical Channel Transistor and Methods of Fabricating the Same. U.S. Patent Number 8785998, filed December 21, 2012, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8785998.PN.&OS=PN/8785998RS=PN/8785998

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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