Patent number 8789169 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a microcomputer, and particularly to a microcomputer having a protection function in a register.
"In recent years, performances of microcomputers have advanced, and functions thereof have also increased in number. For increasing a processing speed of such a microcomputer, it may employ a manner in which a bank structure is formed by arranging two or more general-purpose registers. For example, a structure having two banks is configured to use a bank-0 register by an application program and to use a bank-1 register by an interrupt processing routine.
"When an interrupt occurs when a CPU (Central Processing Unit) using the bank-0 register is executing processing of an application program, it switches the register to the bank-1 register to execute the interrupt processing routine. Thereby, it is not necessary to save contents of the register in a slow memory (stack area), and the interrupt processing can be started fast. Likewise, fast switch or change can be performed when the processing returns from the interrupt processing routine to the application program.
"As a technique related to the above, there is an invention disclosed in Japanese Patent Laying-Open No. 2004-520662 (which will be referred as a 'Patent Document 1' hereinafter). The Patent Document 1 relates to a processor having many registers in a register bank. The resisters have general-purpose registers having a common register name as well as stack point registers. The processor executes a program instruction referring to the common register name, and therefore it has a logic corresponding to programming. This instruction is executed by using the general-purpose register under a first condition and by using the stack point register under a second condition. Therefore, the plurality of registers identified by the same name can be selectively accessed based on the establishment of a specific condition.
"As described above, the use of the bank register allows fast change to the interrupt processing routine as well as fast return from the interrupt processing routine. However, bank-0 registers used by the application program that performs many operations and requires a long processing time are equal in number to bank-1 registers used by the interrupt processing routine that requires a short processing time. Therefore, there is a difference in use efficiency between the registers used by the application program and the registers used by the interrupt processing routine, resulting in a problem that optimization with respect to details of the processing is not performed.
"Further, the general-purpose registers occupy a large part of hardware quantity of the CPU. Therefore, the above bank register structure results in problems of a large chip area and high manufacturing cost.
"In many cases, the operation mode of the interrupt processing is a privilege mode or the like higher in execution privilege than that for executing an ordinary user program, and there is no protection function for the bank register used by the interrupt processing routine. Therefore, there is a risk that contents of the bank register used by the interrupt processing routine are unintentionally rewritten by an application program or a malicious program. Therefore, the conventional CPU suffers from a problem relating to secure use."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An object of the invention is to provide a microcomputer that can optimize efficiency of use of general-purpose registers and can provide a protection function for the general-purpose registers.
"An embodiment of the invention provides a microcomputer including a microprocessor that executes an instruction while accessing a plurality of general-purpose registers. A control unit controls execution of an instruction according to a result of decoding of an instruction code. A GRA register stores an access attribute with respect to each of the plurality of general-purpose registers. A mode storage unit stores a mode for controlling an operation of a CPU. When the control unit requests access to the general-purpose registers, a register access allowance determining circuit determines whether the access to the general-purpose register in question is to be allowed or not, based on the access attribute stored in the GRA register and the mode stored in the mode storage unit.
"In this embodiment, it is determined whether the access to the general-purpose register is to be allowed or not, based on the access attribute stored in the GRA register and the mode stored in the mode storage unit. Therefore, the number of the general-purpose registers to be used can be changed according to the mode, and the efficiency of use of the general-purpose registers can be optimized.
"The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings."
URL and more information on this patent, see: Otani, Sugako; Kondo, Hiroyuki. Microcomputer Having a Protection Function in a Register. U.S. Patent Number 8789169, filed
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