News Column

Patent Issued for Methods and Apparatus for Flip-Chip-On-Lead Semiconductor Package

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventors Sharma, Nirmal (Shrewsbury, MA); Ararao, Virgil (Rutland, MA), filed on April 30, 2008, was published online on July 22, 2014.

The assignee for this patent, patent number 8785250, is Allegro Microsystems, LLC (Worcester, MA).

Reporters obtained the following quote from the background information supplied by the inventors: "As is known in the art, conventional Flip-Chip-On-Leadframe (FCOL) techniques require so-called wafer bumping as an intermediate step between wafer fabrication and leadframe attachment for semiconductor packages. Wafer bumping adds significant cost and delay to the assembly process.

"U.S. Pat. No. 5,817,540 to Wark discloses a method of fabricating FCOL devices and fabricating assemblies. Wark teaches depositing solder on a lead frame by means of dispensing and screen printing and attaching to a bumped wafer with solder reflow. Aside from solder material at lead frame, Wark requires using conductive epoxy, such as silver filled epoxy, for solder bump attachment.

"U.S. Pat. No. 6,482,680 to discloses a FCOL technique requiring dispensing or printing solder on a lead frame, attaching a bump die, and reflowing the solder. Khor teaches the use of a lower temperature melting point solder on the lead frame side than the die bump side, or vice-versa.

"U.S. Pat. No. 6,798,044 to Joshi discloses a conventional method of attachment, such as putting a solder ball or paste on a lead frame, chip attachment, and reflow. Joshi teaches a chip arrangement in which one chip is a controller integrated circuit and the backside of the second chip serves as a drain contact for a MOSFET. Joshi also teaches that the melting point of one bump (flip chip die) is higher (310.degree. C.) than the other (250.degree. C.).

"U.S. Pat. No. 6,828,220 to Pendse et al. discloses a FCOL package and process that includes forming a gold stud-bumping on a die. The attachment method to the lead frame is thermo-compression.

"While the known techniques above may provide some improvement in the art, each requires bumping the die thereby limiting the current-carrying capacity of a bump and also adding significant cost and delay to the assembly process due to the required wafer bumping."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "The present invention provides methods and apparatus to provide a die leadframe connection that eliminates the need for conventional wafer bumping. With this arrangement, semiconductor package assembly is more cost efficient and timely. While the invention is primarily shown and described in conjunction with silicon wafers and dies and certain exemplary fabrication techniques, it is understood that the invention is applicable to semiconductor materials and techniques in general relating to fabricating devices.

"In one aspect of the invention, a method includes placing a conductive material, such as solder paste, on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die, which has an active area, on the first assembly. The method can further include reflowing the conductive material to raise up the die to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. The method can further including surrounding the die with a material to form a third assembly, such as by molding.

"The method can include one or more further features, such as forming a depression in the mask, placing the conductive material in the depression, wherein the protrusion extends into the depression, filling gaps about the reflowed conductive material with an epoxy compound, forming an under bump metallization structure at the active area of the die, and forming a redistribution layer on the die to form a connection point for the active area.

"In one embodiment of the invention, a method includes placing a mask on a lead frame having a protrusion, the mask having a depression into which the protrusion extends, placing solder paste in the depression to form a first assembly, placing a die on the first assembly, the die having an active area, and reflowing the solder paste to raise up the die. The method can further include securing the die to the leadframe such that the solder forms a connection between the protrusion and the active area of the die.

"The method can further include one or more of preparing the active area of the die to provide an under bump metallization structure, molding a package to hold the die and leadframe, filling gaps adjacent the reflowed solder with epoxy, forming the protrusion from the leadframe, and extending the solder paste above the depression.

"In another aspect of the invention, a method includes placing adhesive on a leadframe having a through hole, attaching a die to the adhesive, the die having an active area, placing a solder ball in the through hole, and reflowing the solder ball to form a connection between the active area and the leadframe. The method can further include forming an under bump metallization layer at the active area of the die and forming a redistribution layer on the die.

"In a further aspect of the invention, a semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, a die having an active area coupled to the protrusion by the reflowed solder, a material about the conductive material to secure the die to the leadframe, and an under bump metallization structure on active area of the die.

"The semiconductor package can further include a conductive mask having a depression into which the protrusion extends, wherein the conductive material includes solder paste that raised up the die when reflowed.

"In another aspect of the invention, a device includes a semiconductor package, including a leadframe having a protrusion, a conductive material reflowed to the protrusion, a die having an active area coupled to the protrusion by the reflowed solder, a material about the conductive material to secure the die to the leadframe, and an under bump metallization structure on active area of the die.

"Exemplary device applications include, without limitation, power interface drivers, automotive power and signal processing integrated circuits, safety and security integrated circuits, and power management."

For more information, see this patent: Sharma, Nirmal; Ararao, Virgil. Methods and Apparatus for Flip-Chip-On-Lead Semiconductor Package. U.S. Patent Number 8785250, filed April 30, 2008, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8785250.PN.&OS=PN/8785250RS=PN/8785250

Keywords for this news article include: Electronics, Semiconductor, Allegro Microsystems LLC.

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Source: Electronics Newsweekly


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