News Column

Patent Issued for Method for Encapsulating Electronic Components on a Wafer

August 6, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- STMicroelectronics (Tours) SAS (Tours, FR) has been issued patent number 8785297, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventors are Feron, Marc (Tours, FR); Jarry, Vincent (La Membrolle sur Choisille, FR); Barreau, Laurent (Cinq Mars la Pile, FR).

This patent was filed on October 11, 2012 and was published online on July 22, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates to a method for encapsulating, before scribing, electronic components formed on a semiconductor wafer. It more specifically relates to a method for encapsulating electronic components on which electronic chips are arranged.

"To manufacture an encapsulated electronic chip, a large number of identical electronic components is formed inside and on top of a semiconductor wafer. One or several interconnection levels are then formed above the electronic components to connect the elements of these components together and to connection pads. It may also be provided to arrange electronic chips at the surface of the interconnection stack, on adapted bonding pads. Once these steps have been carried out, the device is encapsulated, then scribed into individual chips.

"To encapsulate electronic components directly on the wafer in which they are formed, known methods provide intermediary steps of gluing of semiconductor wafers, also called handle wafers, at least on one side of the structure. The handle wafers are used to stiffen the structure in different encapsulation steps and during steps of thinning down of the semiconductor wafer in which the components are formed.

"A disadvantage of known methods is that the use of such handle wafers is relatively expensive and constraining. Indeed, such handle wafers are thick semiconductor or glass wafers which are damaged by the gluing and separation operations.

"A method for encapsulating electronic components on which chips may be arranged and secured is then needed, which does not require the use of semiconductor handle wafers while avoiding warpage phenomena."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An object of an embodiment of the present invention is to provide a method for encapsulating electronic components formed inside and on top of a semiconductor wafer, directly on this wafer.

"Another object of an embodiment of the present invention is to provide a method adapted to the encapsulation of electronic components on which chips are arranged and bonded.

"An object of an embodiment of the present invention is to provide a method avoiding problems of warpage of the structure before scribing.

"Thus, an embodiment of the present invention provides a method for encapsulating electronic components, comprising the steps of:

"(a) forming, inside and on top of a first surface of a semiconductor wafer, electronic components;

"(b) forming, on the first surface, an interconnection stack comprising conductive tracks and vias separated by an insulating material;

"© forming first and second bonding pads on the interconnection stack;

"(d) thinning down the semiconductor wafer, except at least on its contour;

"(e) filling the thinned-down region with a first resin layer;

"(f) installing at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads;

"(g) depositing a second resin layer covering the first chips and partially covering the solder bumps;

"(h) bonding an adhesive strip on the first resin layer; and

"(i) scribing the structure into individual chips.

"According to an embodiment of the present invention,

"step (a) further comprises the forming of trenches filled with conductive material on the side of the first surface of the semiconductor wafer;

"step (d) is provided to expose the lower surface of said wafers; and

"step (d) is followed by a step of forming of third bonding pads on the semiconductor wafer, at the level of the trenches filled with semiconductor material and by a step of installing of second chips on the third bonding pads.

"According to an embodiment of the present invention, the first resin layer contains loads having a diameter smaller than 20 .mu.m.

"According to an embodiment of the present invention, the first and second chips are attached on the corresponding bonding regions by second solder bumps.

"According to an embodiment of the present invention, the second solder bumps have a diameter ranging between 20 and 100 .mu.m.

"According to an embodiment of the present invention, the first, second, and third bonding pads are formed of a conductive stack.

"According to an embodiment of the present invention, step (i) is followed by a separation of the adhesive strip.

"The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings."

For the URL and additional information on this patent, see: Feron, Marc; Jarry, Vincent; Barreau, Laurent. Method for Encapsulating Electronic Components on a Wafer. U.S. Patent Number 8785297, filed October 11, 2012, and published online on July 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8785297.PN.&OS=PN/8785297RS=PN/8785297

Keywords for this news article include: Semiconductor, STMicroelectronics, Electronic Components.

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Source: Electronics Newsweekly


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