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"Circuit for Controlling Sense Amplifier Source Node in Semiconductor Memory Device and Controlling Method Thereof" in Patent Application Approval...

August 6, 2014



"Circuit for Controlling Sense Amplifier Source Node in Semiconductor Memory Device and Controlling Method Thereof" in Patent Application Approval Process

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors SEO, Young-Hun (Hwaseong-si, KR); PARK, Chul-Sung (Seoul, KR); LEE, Young-Dae (Yongin-si, KR), filed on December 23, 2013, was made available online on July 24, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Samsung Electronics Co., Ltd.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure herein relates to a semiconductor memory device, and more particularly, to the controlling of a sense amplifier source node in a semiconductor memory device such as a dynamic random access memory.

"Semiconductor memory devices such as dynamic random access memories (hereinafter referred to as 'DRAMs') have been widely used as main memories in electronic systems including computers and portable electronic devices.

"A DRAM, almost by necessity, includes a bit line sense amplifier that detects and amplifies data stored in a memory cell.

"The active operation of a DRAM, for example, a read operation mode or a write operation mode inevitably consumes a power for accessing data. In the case where data access is not performed, for example, in an operation that is not active, a DRAM may have a power down mode for minimally consuming driving current. In order to further reduce power consumption, a DRAM may receive a power down command from a controller even during active operation, which is commonly referred to as an active power down command.

"However, even in the case of an active power down mode, leakage current may continue to flow to a bit line sense amplifier. Thus, power is still consumed."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The present disclosure provides a sense amplifier source node controlling circuit that may minimize or reduce leakage current at a sense amplifier, and a method for controlling a sense amplifier source node according to the same.

"Embodiments of the disclosure provide a circuit for controlling a sense amplifier source node of a semiconductor memory device, the circuit include: a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level; a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.

"In some embodiments, the controller may include: a voltage level amplifying circuit having a first input terminal, and a second input terminal to which a reference voltage is applied; a first switch for switching between the first input terminal and the source node of the sense amplifier in the set operating mode; and a second switch for switching between an output terminal of the voltage level amplifying circuit and the sense amplifier driving signal line in the set operating mode.

"In other embodiments, the sense amplifier may be a bit line sense amplifier including n-type MOS (NMOS) transistors.

"In still other embodiments, the set operating mode may be an operating mode other than an active mode of the semiconductor memory device.

"In even other embodiments, the source driver may include at least one NMOS transistor of which a drain is connected to the source node of the sense amplifier, a gate is connected to the sense amplifier driving signal line, and a source is connected to ground.

"In yet other embodiments, the first and second switches may be MOS transistors that are switched 'on' in the set operating mode and switched 'off' in an operating mode other than the set operating mode.

"In further embodiments, the floating circuit may be a tri-state buffer for applying a sense amplifier enable signal to the sense amplifier driving signal line in an active mode of the semiconductor memory device.

"In still further embodiments, the voltage level amplifying circuit may include a differential amplifier for driving the source node of the sense amplifier to a level of the reference voltage in the set operating mode.

"In even further embodiments, the voltage level amplifying circuit may be shared by one or more memory banks of the semiconductor memory device.

"In yet further embodiments, the circuit may further include an amplifying circuit connected between the voltage level amplifying circuit and the source node of the sense amplifier, for driving the source node of the sense amplifier at a level of the reference voltage or higher.

"In other embodiments of the disclosure, a semiconductor memory device including a sense amplifier is provided. The semiconductor memory device includes a source driver connected between a source node of the sense amplifier and a sense amplifier driving signal line, and configured to control a voltage level of the source node of the sense amplifier; a buffer circuit configured to float the sense amplifier driving signal line in a first operation mode of the semiconductor memory device; and a control circuit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, and configured to control a voltage level of the sense amplifier driving signal line in the first operation mode.

"In some embodiments, the control circuit may include a voltage level amplifying circuit having a first input terminal, and a second input terminal to which a reference voltage is applied; a first switch configured to connect the first input terminal to the source node of the sense amplifier in the first operation mode; and a second switch configured to connect an output terminal of the voltage level amplifying circuit to the sense amplifier driving signal line in the first operation mode.

"In other embodiments, the sense amplifier may be a bit line sense amplifier including n-type MOS (NMOS) transistors.

"In still other embodiments, the first operation mode may be an operating mode other than an active mode of the semiconductor memory device.

"In even other embodiments, the source driver may include at least one NMOS transistor of which a drain is connected to the source node of the sense amplifier, a gate is connected to the sense amplifier driving signal line, and a source is connected to a ground voltage.

"In yet other embodiments, the first and second switches may be MOS transistors that are switched 'on' in the first operation mode and switched 'off' in an operating mode other than the first operation mode.

"In further embodiments, the buffer circuit may be a tri-state buffer configured to apply a sense amplifier enable signal to the sense amplifier driving signal line in an active mode of the semiconductor memory device.

"In still further embodiments, the voltage level amplifying circuit may include a differential amplifier configured to maintain the source node of the sense amplifier at a level of the reference voltage in the first operation mode.

"In even further embodiments, the voltage level amplifying circuit is configured to may be shared by one or more memory banks of the semiconductor memory device.

"In yet further embodiments, the semiconductor memory device may further include an amplifying circuit connected between the voltage level amplifying circuit and the source node of the sense amplifier, and configured to maintain the source node of the sense amplifier at a level of the reference voltage.

"In still other embodiments of the disclosure, a semiconductor memory device is provided. The semiconductor memory device includes a sense amplifier connected between a first bit line and a second bit line, and configured to amplify a voltage difference between a first bit line and a second bit line during a first operation mode of the semiconductor memory device; a source driver connected between a source node of the sense amplifier and a sense amplifier driving signal line, and configured to provide a first voltage to the source node of the sense amplifier during the first operation mode; a control circuit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, and configured to control a voltage level of the sense amplifier driving signal line in response to a voltage level of the source node of the sense amplifier during a second operation mode of the semiconductor memory device different from the first operation mode; and a buffer circuit configured to float the sense amplifier driving signal line during the second operation mode of the semiconductor memory device.

"In still other embodiments of the disclosure, a method of operating a semiconductor memory device having a sense amplifier connected to a first bit line and a second bit line, and a source driver connected to a source node of the sense amplifier, the method includes activating a buffer circuit to provide a first driver control signal having a first voltage level to the source driver from an output node of the buffer circuit; activating the source driver in response to the first driver control signal, such that the sense amplifier is activated; and floating the output node of the buffer circuit and providing a second driver control signal having a second voltage level different from the first voltage level to the output node of the buffer circuit. The second voltage level is responsive to a voltage level of the source node of the sense amplifier.

"According to embodiments of the present disclosure, power consumption due to leakage current of a sense amplifier in an operating mode such as an active power down mode may be minimized or reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain principles of the disclosure. In the drawings:

"FIG. 1 is an exemplary block diagram of a sense amplifier source node control circuit of a semiconductor memory device according to some embodiments;

"FIG. 2 is an exemplary block diagram illustrating a semiconductor memory device of FIG. 1 according to one embodiment;

"FIG. 3 is an exemplary diagram illustrating a part of FIG. 2 according to one embodiment;

"FIG. 4 is an exemplary timing diagram illustrating an operation of FIG. 3 according to certain embodiments;

"FIG. 5 is a diagram illustrating a semiconductor memory device of FIG. 1 according to an exemplary embodiment;

"FIG. 6 is an exemplary timing diagram illustrating an operation of FIG. 5 according to certain embodiments;

"FIG. 7 is an exemplary circuit diagram illustrating a semiconductor memory device of FIG. 5 according to one embodiment;

"FIG. 8 is an exemplary circuit diagram illustrating an expansion of FIG. 5 according to one embodiment;

"FIG. 9 is another exemplary diagram illustrating another expansion of FIG. 5 according to one embodiment;

"FIG. 10 is an exemplary diagram illustrating a modified embodiment of FIG. 9;

"FIG. 11 is an exemplary diagram presented to illustrate the operation of a bit line sense amplifier in FIG. 1;

"FIG. 12 is an exemplary diagram illustrating a connection between the bit line sense amplifier and memory cell blocks of FIG. 11;

"FIG. 13 is an exemplary diagram illustrating a memory cell block of FIG. 12;

"FIG. 14 is an exemplary diagram illustrating a folded bit line structure of the bit line sense amplifier of FIG. 11;

"FIG. 15 is another exemplary diagram illustrating an open bit line structure of the bit line sense amplifier of FIG. 11;

"FIG. 16 is an exemplary block diagram illustrating an electronic system according to certain embodiments;

"FIG. 17 is an exemplary block diagram illustrating a graphic memory system according to certain embodiments;

"FIG. 18 is an exemplary block diagram illustrating a graphic card according to certain embodiments; and

"FIG. 19 is an exemplary block diagram illustrating a computing system including the graphic card in FIG. 18 according to certain embodiments."

URL and more information on this patent application, see: SEO, Young-Hun; PARK, Chul-Sung; LEE, Young-Dae. Circuit for Controlling Sense Amplifier Source Node in Semiconductor Memory Device and Controlling Method Thereof. Filed December 23, 2013 and posted July 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3282&p=66&f=G&l=50&d=PG01&S1=20140717.PD.&OS=PD/20140717&RS=PD/20140717

Keywords for this news article include: Semiconductor, Samsung Electronics Co. Ltd..

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Source: Electronics Newsweekly


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