This patent application has not been assigned to a company or institution.
The following quote was obtained by the news editors from the background information supplied by the inventors: "Capacitive gas sensors are known in the art, a particular example being in the measurement of water vapor (relative humidity). There are a number of configurations associated with these sensors. One configuration uses interdigitated coplanar electrodes of opposite polarity covered by a gas sensitive material in which increasing gas concentration causes an increase in the dielectric constant of such material thereby increasing the dielectric coupling between planar electrodes and thereby increasing the effective capacitance between the electrodes. In the case of the interdigitated electrodes, both electrodes are underneath the top surface of the gas sensitive material, and the dielectric coupling between the planar electrodes occurs by field fringing effects.
"Another configuration employs parallel plate-like electrodes with a layer of gas sensitive material between them such that changing gas concentration changes the dielectric constant of the gas sensitive material and changes the capacitance of the parallel plate capacitor. A parallel plate configuration described in FR2750494 (U.S. Pat. No. 6,450,026) has a top electrode comprised of a highly porous conducting polymer that allows the diffusion of the selected gas through the electrode and into the gas sensitive material. This top electrode material is processed so that it is tightly bonded to the gas sensitive material and is chemically inert and environmentally robust. FR2750494 and U.S. Pat. No. 6,450,026 are incorporated by reference herein in their entirety.
"The capacitance of a capacitive gas sensor is a function of gas concentration, and the capacitance is measured by associated electronics capable of exciting the sensor electrically. The cost of manufacture of the capacitive gas sensors is associated with the physical size of the sensor and the associated electronics, hence it is desirable to provide capacitive gas sensors as small as possible while still achieving desired accuracy and signal to noise ratio. As the size of gas sensitive capacitors is reduced, the gas sensitive capacitors become increasingly susceptible to signal degradation associated with stray capacitances, including parasitic capacitances found in interconnections and in the associated electronics. One way to reduce the effects of parasitic capacitances when using smaller capacitors is to locate the associated electronics as physically close to the sensor as possible.
"Along with reducing the size and therefore the cost of manufacture of the capacitive gas sensors, it is desirable to decrease the size and cost of the associated electronics. Reduced cost of manufacture of the associated electronics can be achieved through the use of application specific integrated circuits (ASICS) which provide all necessary functionality in a small low cost configuration.
"There are commercial devices available in which interdigitated coplanar capacitor electrodes are disposed on top of a section of an ASIC and a gas sensitive material layer is disposed on top of the coplanar sensor electrodes to form a gas sensor. This configuration for ASICs with interdigitated capacitor electrodes has a disadvantage in that if the interdigitated capacitor electrodes are directly over active circuitry in the ASIC, coupling and interference is likely. This results in a need for a larger silicon area to accommodate the sensor electrodes so they are not over active circuitry. Notably, the interdigitated electrodes cannot be shielded from the circuitry-induced stray coupling signals by the addition of a conductive layer intermediate the electrodes and underneath because such a conductive layer would significantly increase the baseline capacitive coupling between the interdigitated sensing electrodes. Since the signal generated by changing gas concentrations in the gas sensitive layer is measured as a changing percentage of capacitance, increasing the baseline capacitance will lower the sensitivity of the device. Another drawback to ASICs with interdigitated electrodes is the undesirable sensitivity of the inter electrode capacitance to foreign material on the top of the gas sensitive material layer. For example, water droplets or small metal particles on the surface of the gas sensitive material layer can significantly alter the dielectric coupling between the electrodes by distorting fringing electric fields generated by the electrodes.
"An alternative device has two separate chips: one chip has a gas sensing capacitor built atop an appropriate substrate and the second chip suitable circuitry. This two chip solution has the advantage of decoupling the production yields, the processes, and the substrate materials used to produce each part. However, these chips must be electrically interconnected using flip chip or wire bonding technology, both of which affect the behavior of the sensing capacitor. Further the cost of electrical and mechanical packaging is greater than the vertically integrated configuration.
"Therefore, there is a need for a smaller and more effective capacitive gas sensor constructed directly on top of an appropriate semiconductor circuitry."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "An embodiment of the present invention relates to a gas sensor assembly comprised of a parallel plate capacitive gas sensor which is constructed directly on top of the passivated surface of a standard semiconductor gas sensor ASIC. The configuration provides the benefits of the parallel plate sensor configuration while allowing the smallest possible sensor size.
"An object of the present invention is to produce a capacitive sensor for measuring gas atop a semiconductor circuit, whereby manufacture thereof is simplified.
"In addition to sensors to be used as gas sensors, the present invention relates to the manufacturing method for these sensors. In a preferred embodiment, this method relates to the successive stacking or formation of a thin metal layer, a gas sensitive layer, and a porous top electrode.
"A method for manufacturing a capacitive sensor on a passivation layer of a semiconductor circuit may comprise: the deposition of a metal layer atop the passivation layer covering the circuitry, the metallization layer patterned to create a bottom electrode, a first trace connecting the bottom electrode to a first bond pad, a landing pad, and a second trace connecting the landing pad to a second bond pad, the bottom electrode being positioned so that it is located over a portion of the semiconductor circuit which contains active circuitry; depositing a gas sensitive layer onto the bottom electrode and the landing pad; creating a via hole through the gas sensitive layer to expose the landing pad; and depositing a porous conductive electrode onto the gas sensitive layer to form a top electrode electrically connected to the landing pad through the via hole, wherein a portion of the top electrode completely overlays a surface area of the bottom electrode and the top electrode connects to the landing pad.
"In an embodiment, a method for manufacturing a capacitive sensor on a passivation layer of an ASIC (510) may comprise: forming a bottom electrode layer and landing pad (520) on a portion of the passivation layer located over active circuitry of the ASIC; forming a gas sensitive layer (530) onto the bottom electrode layer and the landing pad; creating a via hole (540) through the gas sensitive layer to the landing pad; forming a top electrode layer (550) onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer includes filling the via hole with electrically conductive material, thereby forming an electrical connection between the top electrode layer and the landing pad.
"In an embodiment, the process used for forming the bottom electrode layer and landing pad from a metal layer deposited on the passivation layer may comprise a photolithographic process, a photolithographic resist process, or a wet etching process. A spin coating process may be used for forming a gas sensitive layer onto the bottom electrode layer and the landing pad. In an embodiment, the method may further comprise applying a pattern to the gas sensitive layer using a photolithographic technique followed by dry or wet etching processes. The process used for forming the porous top electrode layer onto the gas sensitive layer may comprise screen printing, stencil printing, pad printing, ink jetting, or spin coating. In an embodiment, the method may further comprise forming a molding compound onto the top electrode and the ASIC such that an opening in the molding compound exposes the top electrode to the ambient environment and such that the molding compound covers at least 0.1 mm of the gas sensitive material along all mold compound edges around the opening.
"A gas sensor may comprise: a semiconductor circuit (200) having a top passivation layer (210); a metal bottom electrode (310) on the passivation layer (210) of the semiconductor circuit (200), wherein the bottom electrode (310) is located over an area of the semiconductor circuit that contains active circuitry, a metal landing pad (330) on the passivation layer (210) and electrically separate from the bottom electrode (310); a gas sensitive layer (340) on the metal bottom electrode (310) and metal landing pad (330), the gas sensitive layer (340) having a via (350) defined therethrough; a porous top electrode (320) on the gas sensitive layer (340), wherein an area formed by the porous top electrode (320) completely overlays an area formed by the metal bottom electrode (310), and wherein the porous top electrode (320) is electrically connected to the landing pad (330) through the via (350) in the gas sensitive layer (340); and a first metal trace (390) connecting the metal bottom electrode (310) to a first bond pad (380) and a second metal trace (370) connecting the landing pad (330) to a second bond pad (360). The bottom electrode, landing pad and both connecting traces may be patterned from the same metal layer (for example, by selective patterning). In an embodiment, the semiconductor circuit measures the capacitance of the gas sensitive layer by applying a signal to the metal bottom electrode (310) and measuring the charge displaced by the capacitor through the top electrode.
"In an embodiment, the gas sensor layer (340) covers the first metal trace (390) and second metal trace (370), thereby preventing an electrical short circuit between the porous top electrode (320) and the metal bottom electrode (310) which may be caused by the process used to deposit the top electrode. In another embodiment, the gas sensor may further comprise a mold compound (400) adjacent the porous top electrode (320), the mold compound (400) having an opening (410) for exposing the porous top electrode (320) to the ambient environment, and wherein each side of the opening (410) in the mold compound overlays at least 0.1 mm of the gas sensitive layer (340). In the gas sensor, an area of the porous top electrode (320) may be larger than an area of the bottom electrode (310), thereby enabling the porous top electrode (320) to completely overlay the bottom electrode (310) even if they are misaligned.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1a shows a perspective view of an exemplary embodiment of a capacitive sensor integrated onto a semiconductor circuit including an over-molding compound;
"FIG. 1b shows a perspective view of an exemplary embodiment of a capacitive sensor integrated onto a semiconductor circuit, without an over-molding compound;
"FIG. 1c shows a top view of the exemplary embodiment of an ASIC with a capacitive sensor integrated onto it, including the alignment of the bottom electrode, landing pad, via hole, and the interconnection of the bottom electrode and landing pad to their respective bond pads;
"FIG. 2 shows a partial cross sectional view taken through A-A of FIG. 1c of the width of the short side of the ASIC configuration of FIG. 1c, including the top electrode covering the bottom electrode and making contact through the via hole in the gas sensitive material layer;
"FIG. 3 shows a cross sectional lengthwise view taken through B-B of FIG. 1c of the long side of the ASIC configuration of FIG. 1c, including the overlap of the die packaging material over the connection pads for the capacitor connections.
"FIG. 4 shows a partial cross sectional view taken through A-A of FIG. 1c of the width of the short side of the ASIC configuration of FIG. 1c, including undesired parasitic capacitive coupling from the underlying circuitry to the bottom electrode; and
"FIG. 5 is a flowchart of a process for manufacturing semiconductor circuits with an integrated gas sensor according to an embodiment of the invention."
URL and more information on this patent application, see: Guillemet, Jean-Paul; Drljaca, Predrag; Beeler, Daniel; Gallorini, Romuald; Ducere, Vincent. Capacitive Sensor Integrated onto Semiconductor Circuit. Filed
Keywords for this news article include: Patents, Electronics, Semiconductor, Capacitive Coupling.
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