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Researchers Submit Patent Application, "Low Parasitic Package Substrate Having Embedded Passive Substrate Discrete Components and Method for Making...

July 9, 2014



Researchers Submit Patent Application, "Low Parasitic Package Substrate Having Embedded Passive Substrate Discrete Components and Method for Making Same", for Approval

By a News Reporter-Staff News Editor at Telecommunications Weekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Kim, Jonghae (San Diego, CA); Zuo, Chengjie (Santee, CA); Yun, Changhan (San Diego, CA); Velez, Mario Francisco (San Diego, CA); Shenoy, Ravindra V. (Dublin, CA); Nowak, Matthew M. (San Diego, CA); Carobolante, Francesco (San Diego, CA); Hwang, Kyu-Pyung (San Diego, CA); Kim, Dong Wook (San Diego, CA); Song, Young K. (San Diego, CA), filed on December 19, 2012, was made available online on June 26, 2014.

The patent's assignee is Qualcomm Incorporated.

News editors obtained the following quote from the background information supplied by the inventors: "Various features relate to integrated circuits, and more particularly to integrated circuit package substrates featuring embedded passive discrete components.

"Modern electronic devices, such as mobile phones, laptop computers, tablets computer devices, etc., often include multiple integrated circuits (ICs) and subsystems on a single printed circuit board (PCB). For example, a PCB, such as a 'motherboard,' may include an 'applications processor' responsible for executing much of the calculation intensive processes associated with running applications for the electronic device. Another IC, for example a power management integrated circuit (PMIC), may be responsible for providing power (e.g., one or more supply voltages and currents) from a battery to the applications processor and other ICs of the electronic device. The network of passive and active circuit components, such as wires, traces, vias, other conductive components, capacitors, and/or inductors that ultimately deliver the supply voltages and currents from the PMIC to another IC of the electronic device, such as the applications processor, may be collectively known as the 'power deliver network.'

"The power delivery network (PDN) has losses associated with it due to resistance and other parasitic capacitive and inductive components. Thus, the PDN has an impedance associated with it that varies according to frequency. Minimizing this impedance is imperative for power conservation and energy efficiency of the electronic device. For example, if the applications processor needs a 1 volt nominal supply voltage on chip providing 1 amp of current delivered to it by the PMIC, then the PMIC must output a voltage V.sub.PM=((1.OMEGA.+Z.sub.PDN)/(1.OMEGA.))*V.sub.DD, where Z.sub.PDN is the impedance of the PDN and V.sub.DD (e.g., 1 volt) is the nominal supply voltage of the applications processor. It follows that even a 300 m.OMEGA. impedance at a given frequency results in substantial power loss due to the impedance associated with the PDN.

"FIG. 1 illustrates a cross-sectional, schematic view of an IC package 100 found in the prior art. The IC package 100 includes an IC die 102, such as an applications processor for an electronic device. The IC package 100, and in particular, the IC die 102 is supplied power (e.g., provided nominal supply voltages and currents) from a PMIC (not shown) through a PDN (portions of the PDN external to the IC package 100 are not shown).

"The IC die 102 is electrically coupled to a multi-layer package substrate 104 below it in a flip-chip style. For example, one or more soldering balls 106 may electrically couple the die 102 to metal traces located within a first metal layer 122 of the package substrate 104. The package substrate 104 may be, for example, a four metal layer laminate substrate.

"The package substrate 104 shown includes the first metal layer 122, a second metal layer 124, a third metal layer 126, and a fourth metal layer 128. A plurality of metal vertical interconnect accesses (vias) 108 electrically couple traces of the plurality of metal layers 122, 124, 126, 128 of the package substrate 104 to each other where appropriate. Each of the metal layers 122, 124, 126, 128 are generally separated from one another by a plurality of insulator layers 132, 134, 136 that may be composed of one or more dielectric materials, such as, but not limited to, epoxy resin. In particular, the insulating layer 134 in the middle of the package substrate 104 (e.g., a 'core') is thicker than the other layers and also provides structural rigidity to the package substrate 104.

"Notably, the package substrate 104 includes a cavity 135 (indicated by the dashed line box) within its core 134 that houses an embedded passive substrate (EPS) discrete circuit component, such as a capacitor, resistor, or inductor. In the example illustrated, the core 134 houses a discrete capacitor 110 (e.g., 'decoupling capacitor') that helps reduce the impedance at a range of frequencies of the PDN by balancing inductive contributions due to the IC package 100. However, there also exists a significant amount of inductance L.sub.Trace associated with the conductive path(s) (e.g., vias, traces, etc.) between the decoupling capacitor 110 and the IC die 102 that substantially raises the impedance at another range (e.g., higher range) of frequencies of the PDN. An on-chip capacitor (not shown) located on the IC die 102 helps balance the inductance L.sub.Trace to reduce the maximum impedance of the PDN. Besides balancing the inductance with a capacitor, further reductions in the maximum impedance value of the PDN by directly reducing the inductance value L.sub.Trace itself is desirable. Doing so may consequently reduce the size of the aforementioned on-chip capacitor needed to balance the inductance L.sub.Trace.

"FIG. 2 illustrates a cross-sectional, schematic view of a portion of the package substrate 104 found in the prior art. FIG. 3 illustrates a perspective, schematic view of the capacitor 110 coupled to vias. Referring to FIGS. 2 and 3, the discrete capacitor 110 includes two metal electrodes 202, 204, one at each end of the capacitor 110. For example, each end of the capacitor 110 may be coated with a metal conductor to form the electrodes 202, 204. The electrodes 202, 204 may each have a width w.sub.E and a length l.sub.E, and a top surface 302, 304. The first electrode 202 is electrically coupled to a trace 206 located within the first metal layer 122 by a via 212, and the second electrode 204 is electrically coupled to a trace 208 located within the first metal layer 122 by another via 214 (See FIG. 2). The vias 212, 214 directly couple to the first and second electrodes 202, 204, respectively.

"As shown in FIG. 3, the top surface areas 302, 304 of the electrodes 202, 204 are limited so that only a small number of vias, such as vias 212, 214 can directly couple to them (e.g., one via to each electrode). This limits the performance of the IC 100. Specifically, the parasitic inductance L.sub.Trace and the resistance R.sub.Trace associated with the conductive path from the capacitor 110 to the IC die 102 is relatively high due to, in part, the limited number of vias 212, 214 that are electrically coupled to the capacitor's electrodes 202, 204.

"Moreover, in prior art embedded passive substrate designs, the capacitor's electrodes 202, 204 may electrically couple to traces in only the first and last metal layers 122, 128 (e.g., outer metal layers) of the package substrate 104. Traces that are electrically coupled to power and/or ground nets in the second and third metal layers 124, 126 (e.g., inner metal layers) of the package substrate 104 may not be electrically coupled to the electrodes 202, 204. This may further increase L.sub.Trace and/or R.sub.Trace.

"Thus, there is a need for improved embedded passive substrate (EPS) designs that reduce the inductance and/or resistance associated with one or more conductive paths from an embedded passive substrate discrete component (e.g., decoupling capacitor) to an IC die of an IC package. Reducing this inductance and/or resistance will reduce the impedance of the PDN and increase efficiency of electronic devices featuring ICs having the improved EPS designs."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "One feature provides a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode, the DCC embedded at least partially within an insulator layer, a first via coupling component electrically coupled to the electrode, a first portion of the first via coupling component extending beyond a first edge of the electrode, and a plurality of vias each having a first end coupled to the first via coupling component, at least a first via of the plurality of vias coupled to the first portion of the first via coupling component extending beyond the first edge of the electrode. According to one aspect, the first via coupling component increases an available surface area to which the first ends of the plurality of vias are coupled to. According to another aspect, the plurality of vias includes three (3) or more vias. According to yet another aspect, the plurality of vias each have a second end that are electrically coupled to a first outer metal layer, and at least a second portion of the first via coupling component is positioned within a first inner metal layer, wherein the first inner metal layer is closer to the insulator layer than the first outer metal layer.

"According to one aspect, the first via coupling component is electrically coupled to a first metal trace within the first inner metal layer that is electrically coupled to a power or ground net. According to another aspect, the multi-layer package substrate further comprises a second via coupling component that is electrically coupled to the electrode, a first portion of the second via coupling component extending beyond a second edge of the electrode, at least a second portion of the second via coupling component positioned within a second inner metal layer, the second via coupling component electrically coupled to a second metal trace within the second inner metal layer that is electrically coupled to another power or ground net. According to yet another aspect, the first via coupling component is an extension pad, the extension pad electrically coupled to a first surface of the electrode, the extension pad including at least one of a first overhang region that extends beyond a first edge of the electrode and/or a second overhang region that extends beyond a first widthwise edge of the electrode.

"According to one aspect, the plurality of vias each have a second end that is electrically coupled to a first outer metal layer, a first portion of the extension pad extending beyond the first edge of the electrode, and at least a second portion of the extension pad is positioned within a first inner metal layer, the first inner metal layer closer to the insulator layer than the first outer metal layer. According to another aspect, the extension pad is planar. According to yet another aspect, the extension pad has at least one of a wider width than the electrode or a longer length than the electrode. According to yet another aspect, the extension pad includes both the first overhang region that extends beyond the first edge of the electrode and the second overhang region that extends beyond the first widthwise edge of the electrode, the first widthwise edge perpendicular to the first edge, and the extension pad further includes a third overhang region that extends beyond a second widthwise edge of the electrode, the second widthwise edge positioned on an opposite side of the first widthwise edge of the electrode.

"According to one aspect, the first ends of the plurality of vias are electrically coupled to a first surface of the extension pad, and the at least first via of the plurality of vias is coupled to at least one of the first overhang region and/or the second overhang region. According to another aspect, a second surface of the extension pad is coupled to a first surface of a side plating, the side plating comprised of a metal, and a second surface of the side plating is coupled to a second surface of the electrode, the first surface of the side plating orthogonal to the second surface of the side plating, the first surface of the electrode orthogonal to the second surface of the electrode. According to yet another aspect, the DCC is a multi-layer chip capacitor.

"According to one aspect, the first via coupling component reduces an inductance between the electrode and an integrated circuit die of the integrated circuit package. According to another aspect, the first via coupling component is a side plating having a first surface and a second surface, the electrode having a first surface and a second surface, the at least first via of the plurality of vias coupled to the first surface of the side plating, the second surface of the side plating electrically coupled to the second surface of the electrode, and at least a second via of the plurality of vias coupled to the first surface of the electrode. According to yet another aspect, the first surface and the second surface of the electrode are orthogonal to each other, and the first surface and the second surface of the side plating are orthogonal to each other. According to yet another aspect, the side plating is a metal alloy that comprises at least tin.

"Another feature provides a method of manufacturing a multi-layer package substrate of an integrated circuit package, where the method comprises providing an insulator layer, and a discrete circuit component (DCC) having at least one electrode, embedding the DCC at least partially within the insulator layer, providing a first via coupling component, and a plurality of vias each having a first end, electrically coupling the first via coupling component to the electrode, extending a first portion of the first via coupling component beyond a first edge of the electrode, coupling the first end of each of the plurality of vias to the first via coupling component, and coupling at least a first via of the plurality of vias to the first portion of the first via coupling component that extends beyond the first edge of the electrode. According to one aspect, the method further comprises increasing an available surface area to which the first ends of the plurality of vias couple to using the first via coupling component. According to another aspect, the method further comprises providing a first outer metal layer and a first inner metal layer, electrically coupling a second end of each of the plurality of vias to the first outer metal layer, and positioning at least a second portion of the first via coupling component within the first inner metal layer, wherein the first inner metal layer is closer to the insulator layer than the first outer metal layer. According to yet another aspect, the method further comprises providing a first metal trace within the first inner metal layer, electrically coupling the first via coupling component to the first metal trace, and electrically coupling the first metal trace to a power or ground net.

"According to one aspect, the method further comprises providing a second via coupling component, electrically coupling the second via coupling component to the electrode, extending a first portion of the second via coupling component beyond a second edge of the electrode, providing a second inner metal layer and a second metal trace within the second inner metal layer, positioning at least a second portion of the second via coupling component within the second inner metal layer, electrically coupling the second via coupling component to the second metal trace, and electrically coupling the second metal trace to another power or ground net. According to another aspect, the first via coupling component is an extension pad, and the method further comprises electrically coupling the extension pad to a first surface of the electrode, the extension pad including at least one of a first overhang region that extends beyond a first edge of the electrode and/or a second overhang region that extends beyond a first widthwise edge of the electrode. According to yet another aspect, the method further comprises providing a first outer metal layer and a first inner metal layer, electrically coupling a second end of each of the plurality of vias to the first outer metal layer, extending a first portion of the extension pad beyond the first edge of the electrode, and positioning at least a second portion of the extension pad within the first inner metal layer, the first inner metal layer closer to the insulator layer than the first outer metal layer.

"According to one aspect, the extension pad includes both the first overhang region that extends beyond the first edge of the electrode and the second overhang region that extends beyond the first widthwise edge of the electrode, the first widthwise edge perpendicular to the first edge, and the extension pad further includes a third overhang region that extends beyond a second widthwise edge of the electrode, the second widthwise edge positioned on an opposite side of the first widthwise edge of the electrode. According to another aspect, the method further comprises electrically coupling the first ends of the plurality of vias to a first surface of the extension pad, and coupling the at least first via of the plurality of vias to at least one of the first overhang region and/or the second overhang region. According to yet another aspect, the method further comprises providing a side plating, coupling a second surface of the extension pad to a first surface of the side plating, the side plating comprised of a metal, and coupling a second surface of the side plating to a second surface of the electrode, the first surface of the side plating orthogonal to the second surface of the side plating, the first surface of the electrode orthogonal to the second surface of the electrode.

"According to one aspect, the DCC is a capacitor, and the first via coupling component reduces an inductance between the electrode and an integrated circuit die of the integrated circuit package. According to another aspect, the first via coupling component is a side plating having a first surface and a second surface, the electrode having a first surface and a second surface, and the method further comprises coupling the at least first via of the plurality of vias to the first surface of the side plating, electrically coupling the second surface of the side plating to the second surface of the electrode, and coupling at least a second via of the plurality of vias to the first surface of the electrode. According to yet another aspect, the first surface and the second surface of the electrode are orthogonal to each other, and the first surface and the second surface of the side plating are orthogonal to each other.

"Another feature provides a multi-layer package substrate of an integrated circuit package that comprises a means for insulating, a discrete circuit component (DCC) having at least one electrode, the DCC embedded at least partially within the means for insulating, a first means for increasing surface area electrically coupled to the electrode, a first portion of the first means for increasing surface area extending beyond a first edge of the electrode, and a plurality of vias each having a first end coupled to the first means for increasing surface area, at least a first via of the plurality of vias coupled to the first portion of the first means for increasing surface area extending beyond the first edge of the electrode. According to one aspect, the first means for increasing surface area increases an available surface area to which the first ends of the plurality of vias are coupled to. According to another aspect, the plurality of vias each have a second end that are electrically coupled to a first outer metal layer, and at least a second portion of the first means for increasing surface area is positioned within a first inner metal layer, wherein the first inner metal layer is closer to the means for insulating than the first outer metal layer. According to yet another aspect, the first via coupling component is electrically coupled to a first metal trace within the first inner metal layer that is electrically coupled to a power or ground net. According to another aspect, the package substrate further comprises a second means for increasing surface area that is electrically coupled to the electrode, a first portion of the second means for increasing surface area extending beyond a second edge of the electrode, at least a second portion of the second means for increasing surface area positioned within a second inner metal layer, the second means for increasing surface area electrically coupled to a second metal trace within the second inner metal layer that is electrically coupled to another power or ground net.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 illustrates a cross-sectional, schematic view of an IC package found in the prior art.

"FIG. 2 illustrates a cross-sectional, schematic view of a portion of the package substrate found in the prior art.

"FIG. 3 illustrates a perspective, schematic view of a capacitor coupled to vias found in the prior art.

"FIG. 4 illustrates a cross-sectional, schematic view of an IC package.

"FIG. 5 illustrates a schematic, cross-sectional view of a portion of a package substrate.

"FIGS. 6 and 7 illustrate perspective, schematic views of a discrete circuit component (DCC), extension pads on a top side of the DCC, and vias that electrically couple the extension pads to a first outer metal layer.

"FIG. 8 illustrates a schematic, cross-sectional view of a portion of a package substrate.

"FIG. 9 illustrates a schematic, cross-sectional view of a portion of a package substrate that better illustrates how side platings couple to electrodes.

"FIG. 10 illustrates a schematic, cross-sectional view of a portion of a package substrate.

"FIG. 11 illustrates a schematic, cross-sectional view of a portion of a package substrate where side platings and extension pads couple to electrodes.

"FIGS. 12-21 generally illustrate a process for manufacturing package substrates.

"FIG. 22 illustrates a flowchart for a method of manufacturing a multi-layer package substrate of an integrated circuit package.

"FIG. 23 illustrates various electronic devices that may include an integrated circuit that features a package substrate."

For additional information on this patent application, see: Kim, Jonghae; Zuo, Chengjie; Yun, Changhan; Velez, Mario Francisco; Shenoy, Ravindra V.; Nowak, Matthew M.; Carobolante, Francesco; Hwang, Kyu-Pyung; Kim, Dong Wook; Song, Young K. Low Parasitic Package Substrate Having Embedded Passive Substrate Discrete Components and Method for Making Same. Filed December 19, 2012 and posted June 26, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6525&p=131&f=G&l=50&d=PG01&S1=20140619.PD.&OS=PD/20140619&RS=PD/20140619

Keywords for this news article include: Qualcomm Incorporated.

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