Patent number 8779836 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "This invention relates to integrated circuits, and more particularly, to integrated circuits having power gated functional blocks.
"As the number of transistors included on an integrated circuit 'chip' continues to increase, power management in the integrated circuits continues to increase in importance. Power management can be critical to integrated circuits that are included in mobile devices such as personal digital assistants (PDAs), cell phones, smart phones, laptop computers, net top computers, etc. These mobile devices often rely on battery power, and reducing power consumption in the integrated circuits can increase the life of the battery. Additionally, reducing power consumption can reduce the heat generated by the integrated circuit, which can reduce cooling requirements in the device that includes the integrated circuit (regardless of whether it is relying on battery power).
"Clock gating is often used to reduce dynamic power consumption in an integrated circuit, inhibiting a clock signal from being provided to idle circuitry. While clock gating is effective at reducing the dynamic power consumption, the idle circuitry may nevertheless remain powered on. Leakage currents in the idle transistors lead to static power consumption. The faster transistors (those that react to input signal changes, e.g. on the gate terminals) also tend to have the higher leakage currents which often results in high total leakage currents in the integrated circuit, especially in high performance devices.
"To counteract the effects of leakage current, some integrated circuits have implemented power gating. With power gating, the power to ground path of the idle circuitry is interrupted, reducing the leakage current to near zero. There can still be a small amount of leakage current through the switches used to interrupt the power, but it is substantially less than the leakage of the idle circuitry as a whole.
"Power gating presents challenges to the integrated circuit design. As blocks are powered up and powered down, the change in current flow to the blocks can create noise on the power supply connections. The noise can affect the operation of the integrated circuit, including causing erroneous operation. Additionally, the rate of change in the current flow varies with variations in the semiconductor fabrication process, the magnitude of the supply voltage provided to the integrated circuit, and the operating temperature of the integrated circuit. When these factors slow the rate of change of the current, the delay incurred in enabling a power gated block may increase correspondingly."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry therein when the block is active. Power switches (e.g., transistors) are coupled between the virtual voltage node and a corresponding global voltage node. When the switches are open, the power is not provided to the power gated circuit block. When the power gated circuit block is woken up (i.e. powered on), the power switches may be activated in a sequential manner. As the voltage on the virtual voltage node increases, the rate at which power switches are activated may also be increased. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block, as well as reducing power supply noise. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup while still enabling the wakeup sequence to remain within current and noise specifications.
"In various embodiments, each of the of power switches may be coupled to one of one or more delay chains. Each delay chain may include a number of serially coupled delay elements. And output of each of the delay elements is coupled to a corresponding one of the power switches (e.g., to the gate terminal of a transistor). An enable signal may be applied to a first one of the delay elements and may propagate through the delay chain, with each of the delay elements therein providing a certain amount of delay. As each delay element outputs the asserted enable signal, its corresponding power switch is activated. Thus, as the enable signal propagates through the delay chain, the power switches are sequentially activated. As the voltage present on the virtual voltage node increases, the amount of delay in the delay elements may be reduced, allowing faster propagation of the enable signal. This in turn may accelerate the rate at which the power switches are activated.
"Accelerating the rate of power switch activation may be accomplished in various ways. In one embodiment, reducing the delay of the delay elements (thereby facilitating faster propagation of the enable signal) may be accomplished by the assertion of an indication responsive to circuitry detecting that the voltage magnitude on the virtual voltage node is at or above a certain threshold. Responsive to receiving the indication, the delay elements may reduce the amount of delay provided therein accordingly, thereby accelerating the propagation of the enable signal.
"In another embodiment, each of the delay elements may be coupled to directly receive the voltage from the virtual voltage node. The delay elements may be configured such that the delay provided by each is reduced correspondingly with the increasing voltage on the virtual voltage node. The decrease in the delay may be continuous as the voltage present on the virtual voltage node increases. In another embodiment, each of the delay elements may decrease their respective delay responsive to the voltage on the virtual voltage node meeting or exceeding a threshold. The interval between the first power switch enable and the second power switch enable may be predetermined such that the additional current from the second group of power switches does not cause the total current to exceed the max current and max di/dt during only the first group of power switches are enabled at the fast PVT condition.
"In still another embodiment, a control unit may activate additional delay chains (and thus additional delay elements) in parallel with other, previously activated delay elements. As more delay elements are activated in parallel, more power switches are activated at a given time, thereby increasing the overall rate at which power switches are activated."
URL and more information on this patent, see: Takayanagi, Toshinari;
Keywords for this news article include:
Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC
Most Popular Stories
- Steve Ballmer Files Six-Figure Counterclaim vs. Steve Gordon
- Creepers! Microsoft Buys 'Minecraft' Maker for $2.5 Billion
- Back to School, Even in Immigration Jail
- Hispanic Buying Power Slow but Growing in South
- When to Say No to Investors, Yes to Mentors
- Apple: Record iPhones 6 Orders on 1st Day
- U.S. Factory Output Slowed 0.4 Percent in August
- Is a Mayweather, Pacquiao Big-Money Fight Possible?
- Clinton: 'Fabulous to Be Back' in Iowa
- DOJ Launches Program to Thwart U.S. Extremists