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Patent Issued for Method for Emulating Low Frequency Serial Clock Data Recovery RF Control Bus Operation Using High Frequency Data

July 29, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Gower, James C. (Hawthorne, NJ); Radovcic, Boris (Rockaway, NJ), filed on May 7, 2012, was published online on July 15, 2014.

The patent's assignee for patent number 8780962 is BAE Systems Information and Electronic Systems Integration Inc. (Nashua, NH).

News editors obtained the following quote from the background information supplied by the inventors: "Radio systems have many transceivers for providing radio communications to and from vehicles for example military vehicles and the like. A RF Control Bus (RFCB) is a bidirectional Serializer/Deserializer (SerDes) serial link which transmits Clock and data between transceivers and the external RF hardware such as for example power amplifiers and filters. The RF hardware sends transmit data to an encoder where the data is encoded and the encoded data is send to the transceiver for transmission to other vehicles. Such transceivers can also receive data from other vehicles. Such data is send to RF hardware such as filters after decoding. This invention can be used in any communication link between any type of devices.

"Conventional radio systems use low speed serial transceivers such as for example a Dual Integrated Core Engine Transceiver (DICE-T). DICE-T utilize 10NCJ program which runs at 500 Mbps and has 8b/10b encoding. With such transceivers, the data processing such as encoding and decoding are performed at 500 Mbps data rate. Also certain convention GMR transceiver use a custom RF control bus which is a serial bus operating at low frequencies for example 500 Mbps.

"Programmable logic devices (PLDs) exist as a well-known type of Integrated Circuit (IC) that can be programmed by a user to perform specified logic functions. The PLDs can be of programmable logic arrays (PLAs) or Complex Programmable Logic Devices (CPLDs). One type of PLD, called a Field Programmable Gate Array (FPGA), is popular because of a superior combination of capacity, flexibility, time-to-market, and cost.

"Modern radio systems utilize high speed serial FPGA transceivers such as for example Altera Cyclone IV. The high speed serial FPGA transceivers run at higher frequencies than what is required in the 10NCJ program. For example Altera Cyclone IV utilized in the 10NCJ program run at a minimum data rate of 600 Mbps with 8b/10b encoding. Conventional GMR transceivers utilized on the 10NCJ program are required to run at 500 Mbps with 8b/10b encoding.

"To perform proper encoding and decoding of the RFCB data, a unique approach to the 8b/10b encoding must be implemented which runs the transceivers at 2 Gbps. The Cyclone IV device transceiver does provide hardware 8b/10b encoders and decoders but these cannot be utilized since the transceiver is actually running at 2 Gbps but the encoding must be performed as if the data was 500. Mbps. A need exists, therefore, for a way to emulating low frequency Clock Data Recovery Serial control bus operation using high frequency data."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "The following summary is provided to facilitate an understanding of some of the innovative features unique to the disclosed embodiment and is not intended to be a full description. A full appreciation of the various aspects of the embodiments disclosed herein can be gained by taking the entire specification, claims, drawings, and abstract as a whole.

"It is, therefore, one aspect of the disclosed embodiments to provide for modular electronic systems.

"It is another aspect of the disclosed embodiments to provide for methods for controlling data rates in modular electronic systems for example radio system.

"It is a further aspect of the present invention to provide for a system and method for emulating low frequency Serial Clock Data Recovery control bus operation using high frequency data.

"It is another aspect of the present invention to provide for a method for emulating 500 Mbps RF Control Bus Operation using 2 Gbps Data Rate.

"It is a yet another aspect of the present invention to provide for a system in which FPGAs serial transceivers runs at 2 Gbps and sends out each data bit four times to create an effective data rate of 500 Mbps.

"It is a yet another aspect of the present invention to provide for a system in which FPGA serial transceivers are operated at a high frequency and sends out each data bit a plurality of times to create a low effective data rate.

"The aforementioned aspects and other objectives and advantages can now be achieved as described herein. A system and method for emulating low frequency RF control bus operation using high frequency data is disclosed. In transmission path, the low frequency RFCB transmit data bytes are encoded and then up-sampled. The up-sampled data is then sent to a hardware serializer for transmission. The resulting RF serial output stream appears to the external receiver to be encoded at low frequency even though the transceiver is operating at a higher frequency.

"In reception path, RFCB serial input data is de-serialized and then down-sampled. The down sampled data is then passed through custom byte-alignment logic and finally decoded. The transceivers are operated at high frequency but data is decoded and received as if it were at a lower rate. The FPGA serial transceiver are operated at a high frequency and sends each data bit a plurality of times to create a low effective data rate.

"Current FPGAs such as the Altera Cyclone IV chosen for the 10NCJ program have high speed serial transceivers with 8b/10b encoding but the minimum data rate is 600 Mbps. To perform proper encoding and decoding of the RFCB data, a unique approach to the 8b/10b encoding is implemented which runs the transceivers at 2 Gbps. The Cyclone IV device transceiver does provide hardware 8b/10b encoders and, decoders but these cannot be used since the transceiver is actually running at 2 Gbps but the encoding must be performed as if the data was 500 Mbps. To correct for this, the 8b/10b hardware encoder and decoder are disabled by selecting the `Enable Low-Latency PCS Datapath` option in the Altera Quartus II tool. A custom 8b/10b encoder/decoder running at 50 MHz is implemented using the Quartus II Mega-Wizard to provide the encoding/decoding for the 500 Mbps rate. The custom bit alignment, word alignment, and 8b/10b encoding/decoding logic is implemented outside the transceiver core."

For additional information on this patent, see: Gower, James C.; Radovcic, Boris. Method for Emulating Low Frequency Serial Clock Data Recovery RF Control Bus Operation Using High Frequency Data. U.S. Patent Number 8780962, filed May 7, 2012, and published online on July 15, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8780962.PN.&OS=PN/8780962RS=PN/8780962

Keywords for this news article include: BAE Systems Information and Electronic Systems Integration Inc., Information Technology, Information and Data Loss and Recovery.

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Source: Information Technology Newsweekly


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