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Researchers Submit Patent Application, "Wiring Material and Semiconductor Module Using the Same", for Approval

July 30, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Ando, Takashi (Tokyo, JP); Kajiwara, Ryoichi (Tokyo, JP); Hozoji, Hiroshi (Tokyo, JP), filed on August 13, 2012, was made available online on July 17, 2014.

The patent's assignee is Hitachi, Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "A power semiconductor module composed of an IGBT power device, which performs switching control of a large current, and a diode, which releases an inverse voltage generated at the time of switching, is used in a wide range of fields such as home electric appliances and vehicles as a principal component of a power converter (inverter). Especially, electrically-powered vehicles are promoted and an environment in which the power semiconductor module is used becomes severe, so that this is used under a high-temperature atmosphere in which cooling cannot be sufficiently performed, and current capacity to be controlled is increasing. Therefore, as performance of the power semiconductor module, high reliability for securing normal operation for a long period of time in a usage environment with a large temperature change and a high heat resistance property to resist high temperature of a device due to an increase in heat generation amount from a device associated with large current energization are required.

"In a conventional power semiconductor module, an insulating circuit substrate of ceramic and the like is joined onto a base substrate having high thermal conductivity formed of a Cu-based or Al-based material by soldering and the like, and an electrode surface of a semiconductor device is joined onto Al or Cu circuit wiring forming the insulating circuit substrate by means of soldering. Further, Al or Cu wire wiring is connected to a main electrode terminal on an electrode surface opposite to the surface, which is in contact with a circuit surface, of the semiconductor device (PTL 1, for example). In a conventional structure, a thermal stress applied to a joint part between the semiconductor device and the wiring or between the base substrate and the insulating circuit substrate increases along with the increase in heat generation amount from the device and this generates a crack in a solder layer to break the joint part. A thermal expansion coefficient of the base substrate and a wiring material is five to eight times larger than that of the semiconductor device and the ceramic insulating substrate, so that the stress and a strain of the joint part increase to cause the break of the joint part. Especially, a shearing stress applied on the same plane as a joint interface has a major effect on the break of the joint part. In order to decrease the shearing stress applied on the same plane as the joint interface, it is required to decrease the thermal expansion coefficient of the base substrate and the wiring material to a level comparable to the thermal expansion coefficient of the semiconductor device and the ceramic insulating substrate at least in a joint region.

"As the wiring, the wiring material obtained by mixing a nano power or a nano fiber having a low thermal expansion coefficient with Cu is applied in PTL 1 and the wiring material obtained by impregnating a fiber having a low thermal expansion coefficient with Cu is applied in PTL 2. They are obtained by combination of a material having a low thermal expansion coefficient with an entire conductive material such as Cu. There are C, W, Mo and the like as the material having the low thermal expansion coefficient; electrical conductivity of such materials having the low thermal expansion coefficient is 1/2 or lower of that of Cu, Al and the like conventionally used as the wiring material. Although a specific content rate of the material having the low thermal expansion coefficient is not disclosed in PTLs 1 and 2, it is easily considered that the combination of the material having the low thermal expansion coefficient makes the electrical conductivity lower than that of the conventional wiring material to cause an increase in loss of current."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Technical Problem

"As disclosed in PTLs 1 and 2, a low thermal expansion conductive material is formed by combining a particle having a low thermal expansion coefficient such as ceramic and carbon with a Cu-based or Al-based conductive material. It is easy to realize a property of a low thermal expansion coefficient and high thermal conductivity of the wiring material and it is considered that this may be used as abase substrate having high thermal conductivity. However, it is difficult to use the same as the wiring material of which high electrical conductivity is required capable of decreasing a shearing stress applied on a joint surface to a semiconductor device.

"An object of the present invention is to provide the wiring material satisfying both of high electrical conductivity and improvement in reliability of a joint part by decrease in thermal stress applied to the joint part between the semiconductor device and the wiring material and between the ceramic and the base substrate also in a case in which an ambient temperature of semiconductor equipment increases by an exterior cause or heat generated in the semiconductor device becomes high.

"Solution to Problem

"According to the present invention, there is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber, wherein the core layer is copper or an alloy containing copper, the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than a thermal expansion coefficient of copper, the wiring material has a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.

"Further, the present invention provides a semiconductor module including: a wiring material including a core layer made of metal and a clad layer made of metal and a fiber; a semiconductor device including an electrode; and an insulating circuit substrate including a metal layer, wherein the clad layer is formed of copper or an alloy containing copper and a fiber having a thermal expansion coefficient lower than that of copper, the wiring material has a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, the semiconductor device is mounted on the insulating circuit substrate, an electrode of the semiconductor device and the core layer of the wiring material are connected to each other through the clad layer, and the metal layer of the insulating circuit substrate and the core layer of the wiring material are connected to each other through the clad layer.

"Advantageous Effects of Invention

"According to the present invention, it is possible to provide a wiring material having high electrical conductivity in which reliability of a joint part is improved by decreasing a thermal stress applied to the joint part between a semiconductor device and a wiring material and between an insulating circuit substrate and a radiating base having high thermal conductivity also in a case in which an ambient temperature of semiconductor equipment increases by an exterior cause or heat generated in the semiconductor device becomes high, a radiating base substrate, and a semiconductor module using the same.

"Another object, feature and advantage of the present invention will become clear from following description in examples of the present invention related to the attached drawings.

BRIEF DESCRIPTION OF DRAWINGS

"FIG. 1A illustrates a configuration of a wiring material according to a first embodiment of the present invention.

"FIG. 1B illustrates a structure after heat pressure welding of the wiring material in FIG. 1A.

"FIG. 2A illustrates a configuration of a wiring material according to a fourth embodiment of the present invention.

"FIG. 2B illustrates a structure after heat pressure welding of the wiring material in FIG. 2B.

"FIG. 3A illustrates a configuration of a wiring material of a fifth embodiment of the present invention before paste is applied.

"FIG. 3B illustrates the configuration of the wiring material of the fifth embodiment after the paste is applied.

"FIG. 3C illustrates the configuration of the wiring material of the fifth embodiment after the paste is applied twice.

"FIG. 3D illustrates a structure after heat pressure welding of the wiring material in FIG. 3C.

"FIG. 4A illustrates a method of preparing a sheet material 142 according to a sixth embodiment of the present invention.

"FIG. 4B illustrates the sheet material 142.

"FIG. 4C illustrates a configuration of a wiring material according to the sixth embodiment.

"FIG. 4D illustrates a structure of the sheet material in FIG. 4A after heat pressure welding.

"FIG. 5A is a cross-sectional view of a semiconductor module 200 on which wiring 201 is mounted according to a seventh embodiment of the present invention.

"FIG. 5B illustrates a state in which the wiring 201 is mounted on the semiconductor module 200.

"FIG. 6A is a cross-sectional view of a semiconductor module 300 on which a lead 304 is mounted according to a ninth embodiment of the present invention.

"FIG. 6B illustrates a state in which the lead 304 is mounted on the semiconductor module 304.

"FIG. 7A is a cross-sectional view of an LED module 400 in which a wiring material according to a tenth embodiment of the present invention is used.

"FIG. 7B is a perspective view of the LED module 400.

"FIG. 8A illustrates a configuration of a wiring material according to a third embodiment of the present invention.

"FIG. 8B illustrates a structure of the wiring material in FIG. 8A after heat pressure welding.

"FIG. 9 illustrates a configuration of a semiconductor module according to an eighth embodiment of the present invention."

For additional information on this patent application, see: Ando, Takashi; Kajiwara, Ryoichi; Hozoji, Hiroshi. Wiring Material and Semiconductor Module Using the Same. Filed August 13, 2012 and posted July 17, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4784&p=96&f=G&l=50&d=PG01&S1=20140710.PD.&OS=PD/20140710&RS=PD/20140710

Keywords for this news article include: Electronics, Hitachi, Hitachi Ltd., Semiconductor.

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Source: Electronics Newsweekly


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