No assignee for this patent application has been made.
News editors obtained the following quote from the background information supplied by the inventors: "With the tendency towards miniaturization and multifunctional development of electronic devices, semiconductor devices are forced to be highly integrated. In response to this demand, the so-called Multi-chip Package has been proposed, which involves the integration and stacking of a plurality of chips, as well as the use for limited space.
"FIGS. 1 and 2 illustrate a schematic view of a conventional stacked structure of chips, respectively. FIG. 1 shows that each of chip layer (for example 90a) includes a substrate 901, a dielectric layer 902 formed on the substrate 901, an internal circuit 912 surrounded by the dielectric layer 902, and a metallic layer 911 formed on the dielectric layer 902 connected to the internal circuit 912 through a through hole via 903. When the conventional through silicon via (TSV) 93a and 93b are utilized for two chip layers 90a and 90b in stacking process, the metallic layer 911 is coupled to the internal circuit 912 and engaged to solder bumps 92 on the back side of top chip 90a.
"On the other hand, as shown in FIG. 2, if the upper and lower chip layers 95a, 95b need to be distinguished or selected respectively, it usually add a second metallic layer 96 to achieve the purpose. The disadvantage is the need of at least two metal layers such that manufacturing costs will be increased.
"Currently, many improved stacked structures are proposed, for example, U.S. Pat. No. 7,816,776 described therein, which characterized in that two adjacent chips layers have a symmetrical connection bumps and through hole via so that a parallel path and a serial path can be formed, and with operation of internal circuit to differentiate each chip layer of chips layers."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The purpose of the invention is to reduce necessary number of metal layers provided for distinct circuit and select circuit for 3D chips stacked structure.
"Another purpose of the invention is to propose a simpler process and low manufacturing cost for 3D chips stacked structure.
"To achieve the above-mentioned purpose, one feature of the invention is proposed a three dimensional chips stacked structure, comprising plural chips layers, each of said plural chips layers having plural single-layered conductive members formed thereon, each of said plural single-layered conductive members having a test pad formed thereon, wherein two adjacent said single-layered conductive members for said each of said plural chips layers are structurally formed in minor symmetry with each other along a chip longitudinal direction and an arrangement of said plural single-layered conductive members of two adjacent chip layers are shifted by a predetermined distance, and said plural single-layered conductive members of said two adjacent chip layers communicated through a vertical TSV.
"The proposed scheme may make the input signal via test pad of top chip layer laterally transmitting to adjacent test pad and internal circuit of underlying chip layer via TSV.
"Furthermore, mask design and consequent process can be simplified with respect to a multiple metal layer design and overall dimension of the package and manufacturing cost can be reduced. Thus, the proposed chip stacked structure can realize a compact semiconductor device, wherein mask design for making single-layered conductive members for signal transmitting on different locations becomes quite simplified such that the overall process yield effectively enhances and the manufacturing cost also reduces.
"Each of plural single-layered conductive members includes a pad branch and a non-pad branch, wherein the test pad is configured on the pad branch. For the two adjacent chip layers, at least one the single-layered conductive members of top chip layer extends from the non-pad branch vertically downward to corresponding single-layered conductive member of underlying chip layer by TSV. The plural single-layered conductive members may be L-shaped. Material of plural single-layered conductive members is metal, such as copper.
"Each of plural single-layered conductive members is connected to a corresponding distinct circuit. The corresponding distinct circuit includes an input terminal connected to a drain electrode of a first N-type metal oxide semiconductor field effect transistors (NMOS), a output terminal connected to a lock control circuit, a gate electrode of the first NMOS connected to a reset signal source, a source electrode of the first NMOS connected to ground. The lock control circuit includes a first inverter, a second converter, a second NMOS and a third NMOS. Output terminal is connected to an input terminal of the first inverter and a source electrode of the second NMOS, and an output terminal of the first inverter is connected to an input terminal of the second inverter and a gate electrode of the second NMOS. Output terminal of the second inverter is connected to a gate electrode of the third NMOS, a drain electrode of the second NMOS is connected to a source electrode of the third NMOS, and a drain electrode of the third NMOS is connected to ground. A connecting wire is used to connect to the source electrode of the third NMOS for all lock control circuits.
"Moreover, one of the single-layered conductive members on far left side or right side for each chip layer is connected to a select circuit for controlling the selection of specific chip layer.
"Shape of the test pad may be any shape, such as square. Material of the test pad is for example aluminum, silver or copper.
BRIEF DESCRIPTION OF THE DRAWINGS
"The attached specifications and drawings outline the preferred embodiments of the invention, including the details of its components, characteristics and advantages.
"FIG. 1 illustrates a schematic view of a conventional stacked structure of chips;
"FIG. 2 illustrates a schematic view of another conventional stacked structure of chips;
"FIG. 3 illustrate a schematic view of a stacked structure of two chips layers with distinct circuits in a first preferred embodiment;
"FIG. 4 illustrate a top view of the structure of the FIG. 3 with single-layered conductive members;
"FIG. 5 illustrate a schematic view of a stacked structure of four chips layers with distinct circuits in a second preferred embodiment;
"FIG. 6 illustrate a schematic view of a distinct circuit and its control-related circuit in the second preferred embodiment;
"FIG. 7 illustrate a schematic view of a stacked structure of two chips layers with select circuits in a third preferred embodiment;
"FIG. 8 illustrate a schematic view of a double bi-layers stacked structure of four chips layers with select circuits in a fourth preferred embodiment;
"FIG. 9 illustrate a multilayer stacked structure of chips in a fifth preferred embodiment of the invention."
For additional information on this patent application, see: Huang, Tsai-Yu; Huang, Yi-Feng. Three Dimensional Stacked Structure for Chips. Filed
Keywords for this news article include: Electronics, Patents, Semiconductor.
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