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Researchers Submit Patent Application, "3d Stacking Semiconductor Device and Manufacturing Method Thereof", for Approval

July 30, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor Chen, Shih-Hung (HsinChu County, TW), filed on January 8, 2013, was made available online on July 17, 2014.

The patent's assignee is Macronix International Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The disclosure relates in general to a semiconductor device and a manufacturing method thereof, and more particularly to a 3D stacking semiconductor device and a manufacturing method thereof.

"With the development of semiconductor technology, various semiconductor elements are provided. The semiconductor elements can be installed to realize varied electric performance. Semiconductor elements are widely used in electronic products.

"Under the trends of lightweight, thin, short and small, how to reduce the volume of the semiconductor element or increase the circuit density at a fixed volume becomes an important target in the semiconductor industries."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "The disclosure is directed to a 3D stacking semiconductor device and a manufacturing method thereof.

"According to a first aspect of the present disclosure, a manufacturing method of a 3D stacking semiconductor device is provided. The manufacturing method of the 3D stacking semiconductor device comprises the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are interlaced. N.ltoreq.P.times.Q. N, P and Q are positive numbers. A first photoresister layer is provided. The first photoresister layer covers part of the surface of the stacking structures. The stacking structures are etched P-1 times by using the first photoresister layer as a mask. In each step of etching the stacking structures, the stacking structures are etched for a thickness of one layer. The first photoresister layer is trimmed for a width at each of the 1 to P-2 steps. The first photoresister layer is removed. A second photoresister layer is provided. The second photoresister layer covers part of the surface of the stacking structures. The stacking structures are etched Q-1 times by using the second photoresister layer as a mask. In each step of etching the stacking structures, the stacking structures are etched for another thickness of P layers. The second photoresister layer is trimmed for another width of P layers after each of the 1 to Q-2 steps. The second photoresister layer is removed. N conductive lines are provided. Each conductive line is electrically connected to a contact point of each conductive layer. The first photoresister layer is trimmed along a first direction. The second photoresister layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged in a matrix along the first and the second directions. The included angle between the first direction and the second direction is an acute angle.

"According to a second aspect of the present disclosure, a 3D stacking semiconductor device is provided. The 3D stacking semiconductor device includes N layers stacking structures and N pieces of conductive lines. Each stacking structure includes a conductive layer and an insulating layer. N is a positive number. The conductive layer and the insulating layer are interlaced and stacked. Each conductive line is electronically connected to one contact point of each conductive layer. The contact points are arranged along a first direction to form a P stages stair structure having a single layer interval. The contact points are arranged along a second direction to form a Q stages stair structure having a P stages interval. N.ltoreq.P.times.Q. The contact points are arranged in a matrix along the first direction and the second direction. An included angle between the first direction and the second direction is an acute angle.

"The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiments. The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 shows a 3D stacking semiconductor device;

"FIGS. 2A to 2R show a flow chart of a manufacturing method of the 3D stacking semiconductor device;

"FIGS. 3A to 3B show flow chart of a manufacturing method of a 3D stacking semiconductor device;

"FIGS. 4A to 4C show the change of a photoresister layer during etch and trimming;

"FIG. 5 shows an arrangement of conductive lines and contact points where the conductive lines are connected to the conductive layers;

"FIG. 6 shows an arrangement of conductive lines and contact points where the conductive lines are connected to the conductive layers; and

"FIGS. 7 to 8 show the change of distances between the edge and the contact points."

For additional information on this patent application, see: Chen, Shih-Hung. 3d Stacking Semiconductor Device and Manufacturing Method Thereof. Filed January 8, 2013 and posted July 17, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4795&p=96&f=G&l=50&d=PG01&S1=20140710.PD.&OS=PD/20140710&RS=PD/20140710

Keywords for this news article include: Electronics, Macronix International Co., Macronix International Co. Ltd., Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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