The patent's inventors are Wu, Sunny (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Generally, semiconductor wafers go through many processing steps before a completed die is formed. Some of these processing steps may include lithography, etching, doping, and depositing different materials. The quality of the completed die may depend largely on the accuracy and precision of the processing between different processing steps. For example, misalignment of a gate structure, imprecise doping concentrations, or dielectric layers that are too thick or thin may cause an undesirable amount of leakage current in a transistor or delay in the operation of the circuit.
"Further complicating this problem may be a semiconductor manufacturer's desire to maximize the number of dies produced by the processing steps. In an attempt to maximize productivity, a manufacturer may provide many tools for each processing step. However, each tool may have a behavior different from other tools within the particular processing step. Accordingly, coordinating processing between different tools in different steps may be difficult.
"One typical method for coordinating processing includes dispatching lots from tools to specified respective tools in a subsequent stage to compensate for previous processing. This method may consider only the in-line performance of each tool rather than the final quality of the completed product. Further, this method may also suffer from productivity drawbacks because lots from a first tool in a stage are automatically dispatched to a second tool in a subsequent stage without regard for the availability of the second tool.
"Another typical method attempts to control tool behavior and does not have any set dispatching rules. One example is an Automatic Process Control (APC) that uses in-line measurements after processing a lot to control the tool that previously processed the lot and to control the tool that will immediately subsequently process the lot. This method may consider only productivity, such as minimizing tool idle time, and may ignore the mismatch impact between tools. Thus, the quality of a finished die may be adversely impacted."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
"Another embodiment is a computer program product for providing semiconductor processing control, and the computer program product has a medium with a computer program embodied thereon. The computer program comprises computer program code for providing a first data set for first measured results for a first parameter of processed wafers and a second data set for second measured results for a second parameter of the processed wafers. The first data set comprises first subsets, and the second data set comprises second subsets. Each first subset and each second subset corresponds to one tool in a processing line, and the processing line comprises multiple tools and multiple stages.
"The computer program further comprises computer program code for determining a first residual model and a second residual model for each first subset and each second subset, respectively, and computer program code for determining a first residual vector and a second residual vector for each first subset and each second subset, respectively. A first residual vector entry is based on the first residual model and one of the first measured results of the respective first subset, and a second residual vector entry is based on the second residual model and one of the second measured results of the respective second subset.
"The computer program further comprises computer program code for determining a first residual average and a first residual standard deviation of the first residual vector for each first subset, and a second residual average and a second residual standard deviation of the second residual vector for each second subset, such that each of the multiple tools has a corresponding first residual average, first residual standard deviation, second residual average, and second residual standard deviation. The computer program further comprises computer program code for, for each of the multiple stages, determining an overall index based on the first residual average, the first residual standard deviation, the second residual average, and the second residual standard deviation for each of the multiple tools in the respective stage.
"The computer program further comprises computer program code for identifying at least one of the multiple stages as a key process stage when the at least one of the multiple stages has a corresponding overall index greater than a threshold, and comprises computer program code for forecasting a trend of a wafer based on routing of the wafer through some of the multiple stages through the key process stage. The computer program further comprises computer program code for dispatching the wafer to one of the multiple tools in at least one stage of the multiple stages subsequent to the key process stage in the processing line based on the trend.
"A yet further embodiment is a system for semiconductor processing. The system comprises a processing line comprising a key process stage and a tuning process stage, a tool effect module operable to determine tool effects on an electrical parameter for tools in the key process stage and for tools in the tuning process stage, a trend forecast module operable to determine a trend of the electrical parameter of a wafer that has been processed through the key process stage, and a dispatch control module operable to determine a tuning tool in the tuning process stage that optimally compensates for the trend of the electrical parameter of the wafer and to dispatch the wafer to the tuning tool. The key process stage most affects the electrical parameter of a finished product, and the tuning process stage is subsequent the key processing stage in the processing line."
For the URL and additional information on this patent, see: Wu, Sunny; Tsen, Yen-Di; Lin, Chun-Hsien; Hui, Keung; Wang,
Keywords for this news article include: Electronics, Semiconductor,
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