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Patent Issued for Semiconductor Device with Buried Bit Line and Method for Fabricating the Same

July 30, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Lee, Sang-Do (Gyeonggi-do, KR); Ko, Kyung-Bo (Gyeonggi-do, KR); Lee, Hae-Jung (Gyeonggi-do, KR), filed on September 23, 2011, was published online on July 15, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8779422 is assigned to SK Hynix Inc. (Gyeonggi-do, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to technology for fabricating a semiconductor device, and more particularly, to a semiconductor device with a buried bit line and a method for fabricating the same.

"To increase the amount of memory cells on a chip, patterns may be shrunk. Due to pattern shrinkage, a mask for a mask process may also be smaller in size. Accordingly, a sub-40 nm semiconductor device may adopt an ArF photoresist (PR) layer. However, as an even smaller pattern is desired, the ArF PR layer may not be suitable for a smaller pattern application.

"Therefore, a semiconductor device, such as a DRAM memory device, may use 3-dimensional cell formation techniques.

"A transistor with a planar channel has a physical limit in a leakage current, an on current, and a short channel effect if the semiconductor device is further miniaturized. Therefore, it is difficult to further miniaturize the semiconductor device. However, a transistor using a vertical channel (hereafter, referred to as a vertical channel transistor) may further miniaturize the semiconductor device.

"The vertical channel transistor includes an active region extended vertically over a substrate, a gate electrode (referred to as a vertical gate (VG)) formed on a sidewall of the active region, and a junction formed over and under the active region. The vertical gate is set to be the center of the active region. In such a vertical channel transistor, the vertical gate vertically forms a channel. The lower junction is coupled to a buried bit line (BBL).

"FIG. 1 illustrates a conventional semiconductor device.

"Referring to FIG. 1, a plurality of bodies 13 isolated by trenches 12 are formed on a substrate 11. The bodies 13 correspond to active regions and extend vertically from the surface of the substrate 11. A hard mask layer 14 is formed on the bodies 13. A junction 16 is formed on one sidewall of each body 13. A dielectric layer 15 is formed on both sidewalls of the body 13. A part of the dielectric layer 15 is selectively removed to form an open portion, which exposes the junction 16. A buried bit line 18 is electrically coupled to the junction 16 through the open portion and partially fills the trench 12. A barrier layer 17 is formed to prevent diffusion between the buried bit line 18 and the junction 16.

"In the conventional semiconductor device of FIG. 1, the buried bit line 18 is formed of a metal layer to reduce resistance. In order to form a contact between the junction 16 and the buried bit line 18, a manufacturing process includes a side contact process for exposing one sidewall of the body 13. The side contact process is referred to as a one side contact (OSC) process.

"When a metal layer is used as the buried bit line 18, an ohmic contact may be formed to reduce contact resistance with the junction 16, which is formed of single crystal silicon.

"The ohmic contact 19 may be formed of a silicide layer.

"In this case, however, silicide agglomeration is caused by a thermal process accompanying the silicide process. Such silicide agglomeration may cause a loss of the junction 16, and a junction leakage increases."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An embodiment of the present invention is directed to a semiconductor memory device capable of preventing a loss of a junction caused by silicide agglomeration and a junction leakage, and a method for fabricating the same.

"In accordance with an embodiment of the present invention, a semiconductor device includes: an active body having two sidewalls facing each other in a lateral direction; a junction formed in a sidewall of the two sidewalls; a dielectric layer having an open portion to expose the junction and covering the active body; a junction extension portion having a buried region to fill the open portion; and a bit line coupled to the junction extension portion.

"In accordance with another embodiment of the present invention, a semiconductor device includes: a plurality of active bodies isolated by a plurality of trenches and having two sidewalls; a plurality of junctions formed on a sidewall of the sidewalls of the respective active bodies; a dielectric layer having a plurality of open portions to expose the respective junctions and covering both sidewalls of the active bodies; a plurality of buried bit lines formed over the dielectric layer and partially filling the respective trenches; and a plurality of junction extension portions filling the respective open portions and formed between the buried bit lines and the junctions.

"In accordance with yet another embodiment of the present invention, a semiconductor device includes: a plurality of active bodies isolated by a plurality of first trenches and having two sidewalls; a plurality of junctions formed in a sidewall of the sidewalls of the respective active bodies; a dielectric layer having a plurality of open portions to expose the respective junctions and covering both sidewalls of the active bodies; a plurality of buried bit lines formed over the dielectric layer and partially filling the respective trenches; a plurality of junction extension portions formed between the buried bit lines and the junctions and filling the respective open portions; a plurality of active pillars formed over the respective active bodies and isolated by a plurality of second trenches in a direction crossing the first trenches; a plurality of vertical word lines formed on sidewalls of the active pillars and extended in a direction crossing the buried bit lines; and a plurality of capacitors coupled to upper portions of the respective active pillars.

"In accordance with still another embodiment of the present invention, a method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies isolated by a plurality of trenches; forming a dielectric layer having a plurality of open portions to partially open a sidewall of the sidewalls of the respective bodies and covering the bodies; forming an impurity-doped first conductive layer on the entire surface such that the first conductive layer fills the open portions; forming a plurality of junctions in the sidewalls of the respective bodies contacting with the first conductive layer through a thermal treatment; forming a second conductive layer over the first conductive layer such that the second conductive layer fills the trenches; and recessing the second conductive layer and the first conductive layer to form a plurality of buried bit lines and junction extension portions such that the buried bit lines partially fill the respective trenches.

"In accordance with still another embodiment of the present invention, a method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies isolated by a plurality of trenches; forming a dielectric layer having a plurality of open portions to partially open a sidewall of the sidewalls of the respective bodies and covering the bodies; forming a first conductive layer on the entire surface such that the first conductive layer fills the trenches; recessing the first conductive layer and forming a plurality of buried bit lines which partially fill the trenches while reopening the open portions; forming a second conductive layer over the entire surface of the buried bit lines such that the second conductive layer fills the open portions and the trenches; recessing the second conductive layer and forming a plurality of junction extension portions; and forming a plurality of junctions in the sidewalls of the bodies contacting with the junction extension portions, through a thermal treatment."

URL and more information on this patent, see: Lee, Sang-Do; Ko, Kyung-Bo; Lee, Hae-Jung. Semiconductor Device with Buried Bit Line and Method for Fabricating the Same. U.S. Patent Number 8779422, filed September 23, 2011, and published online on July 15, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8779422.PN.&OS=PN/8779422RS=PN/8779422

Keywords for this news article include: Electronics, SK Hynix Inc., Semiconductor.

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Source: Electronics Newsweekly


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